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| DVB-T Demodulator CXD1968AR Description The CXD1968AR is a 4th generation product in a successful family of DVB-T channel decoders that conforms to the ETSI (EN) 300-744 standard and demonstrates exceptional performance in the current industry regional receiver specifications including Nordig 1.0.2 and IEC (MBRAI) requirements. This state of the art demodulator provides a fully flexible interface compatible with a wide variety of RF tuner solutions from today's common High IF or Low IF architectures to future direct conversion ZIF systems. It offers options to address the cost/performance balance for a range of DVB-T applications from digital only to digital/ analog hybrid systems. Advanced algorithms deliver optimal performance for each system configuration, while options to clock from a variety of tuner sources help to minimize system cost. The highest technical performance is achieved through the implementation of advanced algorithms in synchronization and channel estimation, which result in robust decoding for challenging reception environments such as SFN's and portable reception. It also features an internal auto-acquisition controller that simplifies host software during scanning, and completely eliminates host software intervention during channel acquisition and recovery. In summary, the CXD1968AR is a highly integrated DVB-T channel decoder that provides Sony's highest performance, most flexible configuration and design simplification for today's digital terrestrial receiver designs. Applications: Digital terrestrial set top boxes Digital terrestrial PVRs and recordable DVD players Portable DVB-T receivers Terrestrial IDTV with digital only or hybrid tuner support PC-TV receiver modules DVB-T test equipment Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E06905-PS CXD1968AR Features Fully complies with the ETSI EN 300-744 standard for DVB-T. Operates with all guard intervals, code rates and hierarchical modes Performance designed to Nordig Unified 1.0.2, EBook, DTG, IEC 62002-1/2 and EICTA (MBRAI), and all existing regional DTT specifications Smart auto acquisition controller for minimal host software intervention Operates from low cost tuner reference clock (4 to 20MHz) or standard 20.48MHz crystal for 6, 7 and 8MHz channels High and Low IF input frequency mode compatibility. High IF operation with all common SAW filter frequencies Silicon tuner Zero IF interface support with DC offset, I/Q amplitude correction and I/Q phase imbalance correction Impulse noise cancellation algorithm compliant with DTG and IEC (MBRAI) specification requirements Optimized for SFN channels with pre-cursive or post-cursive echoes, inside or outside guard interval Advanced channel corrector for low multipath channel loss and enhanced time varying channel performance Dual high performance differential 10-bit ADCs Digital filtering for improved ACI protection Digital carrier recovery with 857kHz carrier offset recovery range including up to 3x 1/6MHz transmitter offset Common Phase Error (CPE) correction Special features for fast 2K and 8K acquisition, including fast symbol number detection, automatic mode and guard detection Configurable parallel and serial MPEG2-TS interface with smoothing buffer Fast I2C compatible bus interface provides access to channel SNR, individual carrier SNR, constellation data and TPS data including cell identification bits Very Low operating power consumption (140mW typ.) Standby mode including "Ultra Low" shutdown mode which stops all activity including crystal oscillator to reduce interference with analog TV and multi-tuner input systems Quiet I2C output configuration for tuner control PWM outputs for external AGC control 5V tolerant inputs and outputs 64-pin LQFP package -2- 1. Block Diagram Time, Frequency and Symbol Synchronization TPS Cell Decode & Frame Synchronization Zero IF, Low IF or High IF Input Timing Offset Device Configuration Carrier Offset FFT Window Position AINP_I AINM_I Symbol Resampling 2K/8K FFT ACI & CCI Rejection & Digital AGC Pilot Processing Channel Estimation & Correction A/D 10-bit IF to Baseband Conversion DC Offset Correction I/Q Phase Offset Correction Symbol deinterleave, Demapper, Bit deinterleavel AINP_Q AINM_Q A/D 10-bit IFAGC_I Impulse Noise Canceller Auto Recovery Acquisition Controller Fig. 1. Block Diagram Power Estimation (AGC) -3Power Estimation (AGC) CXD1968AR COFDM Demodulator BER Measurement Data ADC & Logic Clocks OSC, PLL & Clock Generator Clock & Test, JTAG TESTMODE OSCEN INTRPTN RESETN TRSTN 20.48MHz Crystal or 4 to 20MHz Tuner Crystal Reference Input XTALO XTALI TMS TDO TCK TDI ZIF Enable 10/12-bit IF AGC PWM Hi Priority/ Lo Priority Stream Select Forward Error Correction ("FEC") RF_IFAGC_Q 10/12-bit IF AGC PWM 10-bit RF AGC PWM & GPO Viterbi Decoder, Byte Deinterleaver, RS Decoder, Energy Dispersal Quiet I2C TUNERDAT I2C TUNERCLK Interface and Quiet I2C Configuration and Debug/ Monitor Registers Transport Stream Smoothing Buffer MPEG2-TS Interfaces (Parallel & Serial) TSDATA[7:0] TSVALID TSCLK TSSYNC TSERR SDA SCL CXD1968AR CXD1968AR 2. Functional Description The block diagram of the CXD1968AR is shown in Fig. 1. Improvements over CXD1976R and CXD1973Q The CXD1968AR incorporates some enhanced functionality over the CXD1976R. The following improvements offer performance benefits, system cost savings and simplify control of the device: 1. Auto-recovery/acquisition controller This easy to use hardware controller eliminates the processing load on the host processor software during acquisition and will reacquire the channel if the transport stream is lost. The demodulator registers are initialized by host software after power up/reset, then the controller is enabled. The controller automatically acquires the channel selected by the tuner, and continuously monitors for loss of TS or TPS lock and reacquires the channel if necessary. This functionality also reduces host software overhead for zapping, as the host processor need only write a new channel frequency to the tuner - the demodulator will automatically acquire the new channel. The controller can also reduce host processor overhead during channel scanning. Conventional host control of the demodulator is also possible by disabling the controller. 2. Operation from a low cost tuner crystal reference The CXD1968AR can be clocked from a standard 20.48MHz crystal (as in the CXD1976R) or from a tuner generated clock output, typically 4MHz, but can be in the range 4MHz to 20MHz by suitable programming of the PLL registers. 3. Impulse noise cancellation This block compensates for the effects of impulse noise detected in the incoming signal using a proprietary algorithm. 4. Zero IF tuner interface The CXD1968AR includes an optional Zero IF tuner interface to allow use of low cost silicon tuners. This interface includes several new blocks to handle typical signal impairments caused by the Zero IF tuning process: I/Q amplitude imbalance correction (AGC) Mismatches in the I and Q tuner signal paths can cause distortion of the I/Q signal. Dual AGC power estimation blocks individually monitor the I and Q input channels after the ADCs, and drive dual AGC amplifier PWM control outputs, allowing independent control of I and Q channel amplitudes in the tuner baseband amplifiers. The AGC gains of the I and Q channels can be read via I2C. I/Q phase quadrature imbalance correction (QIC) Mismatches in the I/Q quadrature in the tuner local oscillator and signal paths can cause a uniform phase distortion of the I/Q signal across the band. This type of frequency independent I/Q phase imbalance can be corrected by this block. The detected I/Q phase imbalance can be read via I2C. DC offset correction DC offsets in the input signal are estimated and removed by this block. The detected DC offset can be read via I2C. -4- CXD1968AR 5. Improved ACI rejection The Channel Selection Filter (CSF) provides additional rejection of adjacent channel interference, particularly in ZIF mode where there is reduced folding of ACI signals in-band during the ADC sampling process. This can reduce the complexity of the Zero IF tuner baseband filters. 6. Improved performance with echoes outside guard interval The CXD1968AR includes improvements to allow pre-cursive or post-cursive echoes outside the guard interval, to meet the latest DTT specifications. This type of channel can occur in SFN networks. 7. Improved time varying channel performance Performance has been improved in doppler channels to meet the latest DTT specifications. The symbol synchronization algorithm has also been improved to handle "birth-death" echo fading that is more likely in portable reception applications. 8. Improved reading of reserved TPS data There are now separate "odd" and "even" banks of registers that latch the reserved TPS data including Cell-ID occurring on odd and even TPS frames. The length of the valid TPS data can also be read to determine whether Cell-ID and DVB-H signaling is present. 9. Standby power saving mode The standby power has been reduced further. The design can enter and exit standby mode by I2C control. The crystal or clock input is kept running in this mode. 10. Shutdown power saving mode This is a very low power mode, where the crystal oscillator or clock input is stopped by the host processor setting the OSCEN input signal to logic 0. This prevents any clock/oscillator interference affecting analog TV reception. -5- CXD1968AR COFDM Demodulator Core The main processing functions are; 10-bit ADC IF Input Mode Input to the CXD1968AR is a differential IF signal centered at either 4.57MHz or nominally 36.167MHz. The exact IF frequency can be set via the ITB_FREQ_1 and ITB_FREQ_2 registers. An integrated 10-bit A/D converter clocked at 20.48MHz is used to sample the IF signal. Input amplitude is nominally 1V peak-to-peak differential, but can also be set to 0.7V, 1.5V, or 2V peak-to-peak differential using I2C registers. Zero IF (ZIF) Input Mode The I channel uses the same ADC described above for IF input signals. A second 10-bit ADC is used for the Q channel input. Both ADCs sample at 20.48MHz. Input amplitude is nominally 1V peak-to-peak differential, but can also be set to 0.7V, 1.5V, or 2V peak-to-peak differential using I2C registers. Power Estimation (AGC) IF Mode This block monitors the signal level at the output of the ADC and provides a Pulse Width Modulated (PWM) control signal to drive an external (analog) variable gain amplifier (VGA) in the tuner IF stage. This circuit operates as an automatic gain control loop and is normally configured to maximize ADC dynamic range determined by a fixed AGC target value. The enhanced AGC system modifies the AGC gain according to the characteristics of the received channel in order to better cope with interferers. The AGC output voltage is generated as a PWM signal and requires a simple external single pole RC filter to interface with the AGC system. The AGC gain value applied to the external amplifier can be read via a register to assist software RF AGC algorithms. Zero IF (ZIF) Input Mode In ZIF input mode, both the I and Q channels are monitored independently, each driving a separate PWM control signal (IFAGC_I, RF_IFAGC_Q) to allow separate tuner AGC amplifiers to correct for I/Q amplitude imbalances. Other features are similar to IF-mode AGC described above. Automatic Gain Control - External RF This block provides an additional Pulse Width Modulated (PWM) control signal (RF_IFAGC_Q) to drive the variable gain amplifier (VGA) in the tuner RF stage. The output value is set by an I2C register. This feature is only available in IF input mode. In ZIF mode this pin is used by the Q channel AGC PWM output. General-purpose I/O Port The RF AGC pin can be configured to generate a logic level signal in place of the PWM output. This may be used for SAW switching, test output or other user-defined purpose. Alternatively this pin can be programed as a digital input, readable by I2C. The above features are only available in IF input mode. In ZIF mode this pin is used by the Q channel AGC PWM output. IF to Baseband Conversion (ITB) This block translates the received digitized IF signal to complex baseband. Subsequent processing is performed on the complex baseband samples. This block is not used in ZIF input mode. -6- CXD1968AR Symbol Resampling (ITP) This block resamples the complex baseband data to compensate for errors between the transmitter clock and ADC sampling clock frequency thus ensuring the FFT block receives the correct number of samples per OFDM symbol. An all-digital resampling technique is used which eliminates the cost and stability issues associated with internal or external VCXOs. The timing offset can be read from an I2C register allowing external monitoring or control. Frequency Synchronization Loop (CRL) The frequency synchronization loop compensates for intentional transmitter carrier frequency offsets and tuner local oscillator frequency error inherent in the RF to IF conversion process. An all-digital AFC technique estimates the frequency shift using the pilots in the OFDM signal and derotates the I/Q constellation before the FFT process. Frequency offset information can be read from an I2C register. This information may be extracted during a channel scan and subsequently applied to the tuning when pre-selecting (zapping) a channel. The offset range can be programed to allow faster acquisition to broadcast channels even beyond 3 x 166kHz transmitter offset. Scanning under software control is simplified using the extended acquisition range. ACI and CCI Rejection and Digital AGC (CSF + CAS) These blocks filter any residual adjacent channel interference such as NICAM energy leaking through the edges of the SAW filter. The CCI filter can optionally cancel co-channel interference such as vision carrier of an analog TV signal. Digital AGC is also performed to restore a consistent signal after filtering. The CCI filter is automatically applied in the presence of analog co-channel interference, resulting in optimum performance for the received channel. The CSF block provides extra adjacent channel rejection, particularly in ZIF mode where there is reduced folding in-band of ACI signals. COFDM Symbol Synchronization Block (SYR) This block acquires and tracks the position of the FFT sampling window within the OFDM symbol, to allow the FFT to recover the useful carriers including pilot tones with minimal ISI. This block can be programed to perform a fast detection of the guard time interval and mode without using TPS, reducing acquisition time. Alternatively a specific mode and guard configuration can be programed also reducing acquisition times for known channels. The CXD1968AR utilizes a new tracking algorithm which improves symbol tracking in multipath channels, particularly beneficial for reception of SFN broadcasts where there can be echoes outside the guard interval. The algorithm permits acquisition and tracking of pre-cursive and post-cursive echo delays inside and outside the guard interval, and also automatically tracks the "birth" and "death" of echoes occurring at different delays, even if the delay of the main echo path changes. The tracker contains automatic CCI detection and filter selection further optimizing channel reception. FFT Processor This block performs a 2048 or 8192 point FFT on the derotated I/Q samples. Pilot Processing and Common Phase Error (CPE) Correction (SCR and PPM) This block corrects for the phase slope and common phase error present on the carriers due to the FFT trigger point being chosen to minimize ISI. A fast acquisition mode can be programed to allow the device to start outputting transport stream data before a full superframe has been received. Channel Estimation This block estimates a time varying channel frequency response using the pilot carriers embedded in every COFDM symbol. This estimate is then interpolated in the frequency domain and used to correct each of the individual OFDM carriers in the CHC block. This block also estimates the signal and noise power for each carrier, which is used as a reliability estimate to weight the soft decisions of each bit fed to the Viterbi decoder. This feature helps to improve PAL CCI performance where vision and sound carriers can distort nearby COFDM carriers. -7- CXD1968AR Channel Correction (CHC) This block uses the estimated channel frequency response to equalize the carriers against frequency selective attenuation in the channel. TPS Cell Decode and Frame Synchronization (TPS) The Transmission Parameter Signaling (TPS) pilots convey information used to configure the receiver and delimit the COFDM frame boundaries. This block decodes the TPS pilot carriers and generates frame synchronization signals. All the TPS information (shown below) is readable via I2C registers. Length indicator - Needed to read Cell-ID and reserved TPS bits Frame number within superframe (0-3) Constellation (QPSK, 16QAM, 64QAM) Hierarchy information (non-hierarchical, = 1, = 2, = 4) High priority stream code rates (1/2, 2/3, 3/4, 5/6, 7/8) Low priority stream code rates (1/2, 2/3, 3/4, 5/6, 7/8) Guard interval (1/32, 1/16, 1/8, 1/4) Transmission mode (2K, 8K) All TPS bits reserved for future use (S40-S53), such as Cell ID and DVB-H indicator bits Symbol Deinterleaver (SDI) The transmitter interleaves the QAM symbols to ensure that a given QAM symbol is mapped to a different carrier in each COFDM symbol, to avoid a succession of errors at the Viterbi decoder input due to frequency selective attenuation involving several adjacent carriers. The symbol deinterleaver deinterleaves the corrected carriers from the channel estimation and correction blocks together with the reliability information. Symbol Demapper (DMP) The demapper processes the complex symbols and reliability information issued from the symbol deinterleaver, generating weighted soft decision information for each bit. Bit Deinterleaver (BDI) Depending upon the QAM level used, the transmitter splits up the input data bits into 2, 4 or 6 streams which are then interleaved to ensure that consecutive input data bits are not mapped to the same QAM symbol. The bit deinterleaver reverses this process by deinterleaving the soft decision information for each bit from the Symbol Demapper. In hierarchical mode, this block outputs a high priority and low priority bit stream. In non-hierarchical mode, a single bit stream is output. Low/High Priority Stream Select For hierarchical transmissions, this block selects (via an I2C register) either the high priority or low priority transport stream for processing by the remainder of the decoder as shown in Fig. 2. -8- CXD1968AR Forward Error Corrector (FEC) LOCK Flag BER Figures Lost Lock Flag SYNC Byte Lock Detection BER Measurement Transport Stream Lock Detection & ISYNC Detect FEC Register Bank (FRB) Inverted SYNC Flag Bits from High/Low Priority Select Viterbi Decoder BB0 SYNC Flag Byte Deinterleaver BB1 SYNC Flag ReedSolomon Decoder BB2 SYNC Flag Energy Dispersal Removal BB3 SYNC Flag Baseband Transport Interface Stream Data Fig. 2. FEC Block Diagram (Viterbi decoder to transport stream output only) Viterbi Decoder (VIT) The Viterbi decoder uses the weighted soft decision data to perform a maximum likelihood estimation of each received bit. All code rates in the ETSI (EN) 300 744 standard are supported. Bit error rates at the input and output of this decoder can be monitored via the I2C bus. The serial bit stream output of the decoder is converted into byte wide format by a serial to parallel converter before it is passed to the byte deinterleaver. Sync Byte Lock Detection This block detects the MPEG2-TS sync bytes or inverted sync bytes at the output of the Viterbi decoder in order to ensure correct synchronization of the byte deinterleaving and correct identification of the inverted sync bytes. Byte Deinterleaver This block implements standard DVB compatible Forney type convolutional deinterleaving (I = 12, N = 204, M = 17, where M = N/I). Burst errors are split up across multiple MPEG2-TS packets, which increases the probability of successful Reed-Solomon error correction. Reed-Solomon Decoder This block is a DVB compatible (255,239) Reed-Solomon decoder implementing the standard DVB shortened (204,188) code using a (GF generation polynomial p(x) = x8 + x4 + x3 + x2 + 1) to correct up to t = 8 erroneous bytes per MPEG2-TS packet. R/S decoding errors occurring when more than 8 bytes are in error are used to calculate error statistics, and are also signaled on the MPEG2-TS interface TSERR signal. Transport Stream Lock Detection and Sync Byte Inversion This block detects the MPEG2-TS sync bytes and inverted sync bytes after correction by the R/S decoder in order to provide a more resilient lock detection mechanism which is called Transport Stream Lock in this document. Operation is similar to the sync byte lock detection block described above. This block also detects the inverted sync bytes, which are then inverted by the energy dispersal block. Energy Dispersal The error-corrected bytes are derandomized with a 15-stage PRBS (Pseudo Random Binary Sequence) generator, with polynomial 1 + X14 + X15 and start-up sequence "100101010000000". Sync bytes are not derandomized, and when an inverted sync byte is detected, every 8th packet, the PRBS resets to the start-up sequence and the sync byte is reinverted. The derandomized data is output through the TSDATA pins, along with a data clock and synchronization signal. -9- CXD1968AR MPEG2-TS Baseband Interface This block provides parallel and serial MPEG2-TS outputs. Due to the guard intervals and redundancy in the received COFDM signal, the MPEG2-TS output data can be bursty. MPEG2-TS packets can cross COFDM symbol boundaries resulting in periodic gaps between successive bytes in an MPEG2-TS packet. For this reason, the parallel and serial MPEG2-TS interfaces allow several different configurations of the TSCLOCK, TSERR, TSSYNC and TSVALID signals as described below. This block also smoothes the TS output in the time domain. This enables the serial interface to output data at the average rate rather than the peak rate and also reduces jitter on the PCR embedded in the TS. Transport Stream Smoothing When enabled, the transport stream smoothing function can operate in one of two modes: Automatic Mode, where the degree of smoothing is determined by reading the TPS data embedded in the DVB ensemble. Manual Mode, where the degree of smoothing is set by programming an I2C register. In manual mode the quality of the smoothing depends on how the I2C register is programed. The effect of the transport stream smoothing function is different in parallel and serial modes: Parallel Mode: The frequency of the TSCLK output is almost the same as the data rate; there will be few gaps in the transport stream output (signaled by either TSVALID going inactive or a gated TSCLK - see below). These gaps will never be within the 188 valid data bytes in a packet. This is because TSCLK is slightly fast, because allowances have to be made for timing offsets between the transmitter and receiver. Serial Mode: The frequency of the TSCLK output is fixed at 41MHz (40.96MHz if a 20.48MHz crystal is used), irrespective of the data rate. The valid data outputs are spread evenly, but there will be gaps output (signaled by either TSVALID going inactive or a gated TSCLK - see below). These gaps will never be within a byte. Parallel Output Mode Fig. 3 illustrates the relationship between the CXD1968AR MPEG2 transport stream interface signals. The transport stream clock (TSCLK) can be programed for the external device to sample on the rising or falling edge (only rising edge sampling is shown here). The interface supports a number of additional signals, which indicate the integrity of the output data. Once the demodulator has achieved lock to the MPEG2 sync byte, the transport stream interface is activated. Fig. 3 shows a complete MPEG2 packet consisting of a sync byte (47h) data bytes (dd) and Reed-Solomon bytes (rr). Note that all the interface control signals have individual programmable polarity; active high signals are shown in the diagram. TSCLK has two operating modes selected via I2C: Continuous Mode, where the clock runs continuously during all 204 bytes of each packet, and during gaps between bytes, thus requiring the external device to use TSVALID to validate the 188 data and sync bytes. Data Only Mode, where the clock is activated only for each of the valid data bytes and remains inactive at all other times. There are two further sub-modes in TSCLK Data Only Mode selected via I2C: 188 Mode, where TSCLK is active for the first 188 bytes in the TS packet. 204 Mode, where TSCLK is active for all 204 bytes in the TS packet. TSDATA[7:0] is the byte wide MPEG2-TS data with programmable MSB/LSB ordering. The default is TSDATA7 being the MSB. TSVALID identifies the data portion of transport stream packet (excludes R/S bytes). TSVALID has two operating modes depending on the TSCLK operating mode: TSCLK in Continuous Mode: TSVALID is set active for 1 TSCLK for each of the 188 data and sync bytes. TSCLK in Data Only Mode: TSVALID is set active during the 188 byte data portion of packet and inactive during the 16 Reed-Solomon bytes. - 10 - CXD1968AR TSSYNC is set active during the MPEG2 sync byte and reset inactive for the remainder of the packet. TSERR is only set active if the transport stream packet error flag is set within the MPEG2 TS. This signal indicates that the Reed-Solomon decoder was unable to correct all errors in the packet. There are 2 programmable modes for this signal: Whole Packet Mode: Active during the entire 204-byte packet. Data Only Mode: Active during the 188-byte data portion of packet and inactive during the 16 ReedSolomon bytes. TSCLK Continuous Tsu TSCLK Data Only 188 GAP TSCLK Data Only 204 GAP Th GAP TSDATA [7:0] rr 47h dd dd dd rr rr rr rr 47h dd TSVALID (with TSCLK Continuous) TSVALID (with TSCLK Data Only) GAP TSSYNC TSERR Whole Packet TSERR Data Only Gaps will not appear within the 188 valid data bytes (dd) in parallel mode if TS smoothing is enabled. Fig. 3. MPEG2 Transport Stream Output Configurations (Parallel Mode) - 11 - CXD1968AR Serial Output Mode Fig. 4 illustrates the relationship between the CXD1968AR MPEG2 transport stream outputs when programed into serial output via I2C. The TSCLK can be programed for the external device to sample on the rising or falling edge (only rising edge sampling is shown here). The interface supports a number of additional signals, which indicate the integrity of the output data. Once the demodulator has achieved lock to the MPEG2 sync byte, the transport stream interface is activated. Data bits are shifted out on TSDATA0 or TSDATA7 (selectable via I2C), starting with the sync byte (47h). The remaining TSDATA signals are held inactive to reduce noise. The data bit order can be programed as MSB first or LSB first via an I2C register. The frequency of the TSCLK output is 41MHz (40.96MHz if a 20.48MHz crystal is used) provided transport stream smoothing is enabled. It is recommended that the serial interface is only used with transport stream smoothing enabled. Fig. 4 shows a complete MPEG2 packet consisting of a sync byte (47h) data bytes (dd) and Reed-Solomon bytes (rr). Note that all the interface control signals have individual programmable polarity; active high signals are shown in the diagram. TSCLK has two operating modes and polarity selected via I2C. The operating modes are: Continuous Mode, where the clock runs continuously at a rate of 1 cycle per bit for all 204 bytes of each packet and during the gaps between bytes thus requiring the external device to use TSVALID to validate the 188 data and sync bytes. There are never any gaps between successive bits of the same byte. Data Only Mode, where the clock is activated only for 8 pulses on each byte output for each of the valid data bytes, and remains inactive at all other times. There are never any gaps between successive bits of the same byte. There are two further sub-modes in TSCLK Data Only Mode selected via I2C: 188 Mode, where TSCLK is active for the first 188 bytes in the TS packet. 204 Mode, where TSCLK is active for all 204 bytes in the TS packet. Serial data can be output from either TSDATA0 or TSDATA7 under the control of I2C. MSB/LSB ordering is also selectable via I2C. TSVALID identifies the data portion of transport stream packet (excludes R/S bytes). TSVALID has two operating modes selected depending on the TSCLK operating mode: TSCLK in Continuous Mode: TSVALID is set active for 8 TSCLK periods for each of the 188 data and sync bytes. TSCLK in Data Only Mode: TSVALID is set active during the 188 byte data portion of packet and inactive during the 16 Reed-Solomon bytes. TSSYNC identifies the first byte in the transport stream packet and has two operating modes selectable by I2C: Byte Mode, where TSSYNC is set active for the first byte of the transport stream packet and reset inactive for the remainder of the packet. Bit Mode, where TSSYNC is set active for the first bit of the MPEG2 sync byte and reset inactive for the remainder of the packet. TSERR is only set active if the transport stream packet error flag is set in the MPEG2 TS. This signal indicates that the Reed-Solomon decoder was unable to correct all errors in the packet. There are 2 programmable modes for this signal: Whole Packet Mode: Active during the entire 204-byte packet. Data Only Mode: Active during the 188-byte data portion of packet and inactive during the 16 ReedSolomon bytes. - 12 - CXD1968AR TSCLK Continuous TSCLK Data Only 188 TSCLK Data Only 204 TSDATA0 76543210 X 76543210 X XXXXXXXX X 76543210 76543210 X 76543210 X 76543210 rr TSVALID (with TSCLK Continuous) TSVALID (with TSCLK in Data Only Mode) TSSYNC Bit Mode 47h dd dd rr rr 47h rr 47h dd dd rr rr 47h rr 47h dd dd rr rr 47h TSSYNC Byte Mode TSERR Whole Packet TSERR Data Only This Tlos TSCLK Tsus TSDATA0 Ths Tclks Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X TSVALID (with TSCLK Continuous) TSVALID (with TSCLK in Data Only Mode) TSSYNC Bit Mode TSERR Fig. 4. MPEG2 Transport Stream Output Configurations (Serial Mode) - 13 - CXD1968AR Interrupts The INTRPTN pin can be switched active low on the occurrence of one or more of the following conditions: Receipt of a TPS block Received TPS parameter change Receipt of a TPS block with a bad BCH check Change of AGC lock status TPS receive frame error Completion of FFT processing of the current symbol Occurrence of MPEG2 transport stream lock Loss of MPEG2 transport stream lock Occurrence of FEC (sync byte) lock Occurrence of errored second Occurrence of severely errored second Occurrence of more than 8-byte errors in transport stream packet (rejected codeword) TS smoothing circuit under/overflow Separate interrupt enable and status bits for each interrupt are provided. An interrupt condition can be latched without generating INTRPTN to allow interrupt polling. Diagnostic Interface There is a diagnostic interface, which enables the following to be read using the I2C interface: Mean signal-to-noise ratio across all carriers Signal-to-noise ratio on each carrier Real and imaginary components of each carrier after channel correction Real and imaginary components of the channel estimate for each carrier Estimated noise power for each carrier BER Measurement The CXD1968AR FEC includes comprehensive signal quality measurement logic. The current estimated Bit Error Rate (BER) of the received signal at various points in the receiver and a measure of the long-term signal quality are both available via I2C registers. It is also possible for a highly accurate BER to be measured, with a transmitted sequence of NULL MPEG2 packets in accordance with ETSI TR 101 290 v1.2.1. The measurements available are; 1. Pre-Viterbi decoder BER (can be measured with real live MPEG2 datastreams) 2. Post-Viterbi BER can be measured in two ways: Using live MPEG2 datastreams. This is an exact measurement provided each transport stream packet contains no more than 8-byte errors, and is an estimated measurement if the packet contains 8 or more errors. Using MPEG2 NULL packets. This is an exact measurement based on comparison between the received packet and a stored MPEG2-TS NULL packet, and allows more than 8-byte errors in the received packet to occur without introducing inaccuracies in the BER measurement. 3. 4. 5. 6. Post R/S decoder BER (requires MPEG2-TS NULL packets to be sent) Number of rejected codewords per second (R/S decoder errors due to more than 8-byte errors occurring) Interrupt on occurrence of errored second (ES, at least one rejected codeword/second) Interrupt on occurrence of severely errored second (SES, n or more rejected codewords in a second where n is a programmable threshold) - 14 - CXD1968AR Tuner Control Interface The Quiet I2C Module contained within the CXD1968AR allows the simple connection of slow I2C slave(s) to a 400kHz master by providing the necessary logic to guarantee all of the timing parameters for the slower device. If the slave is slower than 400kHz then it can use the slave acknowledge mechanism of holding the clock low between high phases. The Quiet I2C Module does not provide for multi-master arbitration. In order to satisfy the tuner's requirement that the bus is normally quiet, the slave interface may be enabled or disabled. PLL Operation Internal clock signals are derived from an all-digital PLL. The functionality of this circuit has been extended to allow operation with an optional external clock signal. A typical application could be to use a 4MHz clock provided by the RF tuner, permitting the removal of the 20.48MHz crystal and components. The following diagram illustrates the configuration used to generate the internal clock signals when a 20.48MHz crystal is present. FIN R[4:0] Range: FREF 4 to 20MHz Range: & 20.48MHz Programmable 2 to 8MHz Reference Divider OD[1:0] Charge Pump Loop Filter VCO FOUT Programmable Output Divider Programmable Feedback Divider FVCO Range: 200 to 400MHz Divide by 2 F[8:0] In this example the clock source FIN is obtained from the crystal oscillator, running at a nominal 20.480MHz. The reference divider R[4:0] is set to /5 which in combination with the fixed /2 results in FREF of 2.048MHz. The feedback divider F[8:0] is set to /80 which in combination with the fixed /2 results in the VCO, FVCO running at 327.68MHz (not accessible to the user). The output frequency FOUT is divided by 4, OD[1:0] to give an 81.92MHz clock to the clock divider logic in the demodulator core. Refer to the registers PLL_FODR (0xA7) and PLL_F (0xA8) for detailed programming information and a table of register settings for the supported external clock and crystal frequency combinations. The application note EAN-0066 provides programming examples. Note) The internal clock frequency of 20.48MHz can change to 20.50MHz for some clock configurations. This will require alternative values of ITB_FREQ and TRL_NOM_RATE. - 15 - CXD1968AR JTAG Test Interface Test Mode The JTAG interface consists of five test pins available on the CXD1968AR. These are used only for embedded test and should be inactive for normal device operation. These pins are; TRSTN TDO TDI TMS TCK Pin 34 Pin 30 Pin 31 Pin 32 Pin 29 The JTAG interface conforms to the "IEEE 1149.1 Joint Test Action Group (JTAG)" standard. The following instructions are available: Instruction BYPASS EXTEST SAMPLE/PRELOAD Code 1111 0000 0001 Normal Device Operation The input functions of this group have very weak internal pull-ups present on the pins. This is primarily to ensure that these pins cannot be left floating, a condition which could cause the device to draw excessive current. Under circumstances that may be influenced by board layout and supply power-up effects, the JTAG circuit can be inadvertently activated in parallel with the normal operation of the demodulator. This results in the main I2C bus locking. This condition is readily identified but cannot be resolved without either a hardware reset or power-down. Once the main I2C bus has locked it is not possible to communicate with the chip, hence only an external reset will permit resumption of normal operation. If JTAG functionality is not required, the interface should be disabled to ensure this mode cannot be initiated. This is implemented by forcing the test block into permanent reset. The TRSTN and TCK inputs should be grounded. For users who wish to implement the JTAG test mode in their equipment, it will be unacceptable to permanently ground the TRSTN and TCK inputs. It is suggested that these inputs are pulled to ground by an external resistor. A pull-down value of 10k is recommended, however the choice of value will depend upon the driver circuit and speed of operation. This is illustrated in the application circuit in section 4. - 16 - CXD1968AR 3. Description of Operation This section describes the operation of the CXD1968AR DVB-T COFDM demodulator IC and how to make use of these features when operating the device. It does not give a detailed description of the enhanced modes of operation, users should refer to the separate engineering application notes for additional information about these configurations and uses. The following descriptions apply to the CXD1968AR used with a tuner providing a High IF signal at a nominal frequency of 36.1667MHz. Contact Sony for configuration recommendations when operating with Low IF (4.5MHz) or Zero IF at the e-mail support address CXD1968_support@eu.sony.com EAN-0065 and EAN-0066 are intended to assist users familiar with its predecessor the CXD1976R, and intend to make the transition to the CXD1968AR. Engineering Application Notes are available for download to registered users from the Sony Technical Library http://www.sonybiz.net/semiconductor. Processor Interface The CXD1968AR must be configured by a host controller, which is required for initialization and to monitor its performance by writing and reading the CXD1968AR internal registers. The CXD1968AR controller interface is a serial interface which corresponds to the I2C standard. The I2C interface supports access at bit rates up to 400kbit/s. The I2C uses an 8-bit address: The first 6 significant bits relate to the device type and are fixed at 110110. A single external address pin A0 is provided so that 2 different I2C slave address locations can be used. This permits multiple front-end configurations, for instance PVR application. The least significant bit is set to "1" for a write and "0" for a read. Address pin A0 0 1 CXD1968AR I2C address Binary 1101 100 R/W 1101 101 R/W Hexadecimal D8h + R/W DAh + R/W Examples used in this document assume an I2C address of 0xD8. Reference to 0xD8 indicates a write instruction and to 0xD9 indicates a read instruction. Multibyte Reads Some registers contain fields more than 8 bits which are each accommodated across two or three registers. It is therefore possible for the field value to change in the time between two reads from the register pair. When a "1" is written to the freeze bit in the PIR_CTL register (whether it was previously "0" or not), the field values are latched and the multibyte value can be read without fear of reading a corrupt value. With the freeze bit set to "0" the data within the fields changes dynamically. - 17 - CXD1968AR Tuner Quiet I2C Interface The tuner I2C interface allows the I2C interface to the tuner to be isolated from the host I2C interface to the rest of the system. This uses on-chip switching. When an I2C master wants to send data to the tuner, it must first enable the slave interface before sending the data. To enable the tuner Quiet I2C interface the enable_quiet_I2C bit must be set in the TUNER_CTRL5 register (bit 7 at register address 0xAF). The normal sequence of operation is; 1. Set the enable_quiet_I2C bit in TUNER_CTRL5. 2. Send/Receive the tuner I2C address and data as if it were being accessed directly by the host controller. 3. Reset the enable_quiet_I2C bit in TUNER_CTRL5. Example: 0xD8 0xC0 0xD8 0xAF 0xAA 0xAF 0x80 0xBB... 0x00 ; enable quiet I2C bus ; read/write any number of messages ; to tuner @ address 0xC0 for example ; disable quiet I2C bus Reset There are three types of reset. A hard reset is initiated at power up; cold and warm resets are initiated by programming the RST_REG register (below). With cold and warm resets, the host controller determines the type of reset and which parts of the CXD1968AR are to be reset. Hard Reset A hard reset is applied to all the CXD1968AR logic. A hard reset is initiated at power up by driving the RESETN pin low for more than 28ns. When the CXD1968AR is powered up, it must be hard reset. Whenever a hard reset occurs, the PLL will be out of tune. It must not drive logic until it has tuned. This is prevented by the reset to any PLL clocked logic being held in reset after a hard reset. The host controller must configure then enable the PLL output and release this reset after the PLL has tuned. The PLL output is enabled by setting the PLL_op_enable bit in the PLL_CONTROL register. The reset is released when the host controller resets the "hard" bit of the RST_REG register. The PLL tunes in 500s. Cold Reset A cold reset is initiated by setting the cold bit in the RST_REG register, and resets any modules that are selected by the RST_REG register, including their I2C registers. Warm Reset A warm reset is initiated by setting the warm bit in the RST_REG register, and resets any modules that are selected by the RST_REG register, excluding their I2C registers. - 18 - CXD1968AR COFDM Demodulator Configuration While there are many registers which can be programed to configure the COFDM demodulator, there are only a few which must be programed to setup the interface to the tuner. The following must be configured: Configure clock, PLL and ADC Set ITB frequency for chosen IF frequency Set TRL nominal rate for current channel bandwidth IF AGC sense if required Input spectrum inversion if required Clock, PLL and ADC Configuration This means setting the clock mode for operation using the internal oscillator (crystal) or from an external clock source (tuner). PLL divider settings according to the oscillator or clock frequency. The ADC powersup in dual channel mode (defaults to ZIF input), for IF mode the unused Q channel is then turned-off. A description has been given in section 2, PLL Operation, with reference to the application note EAN-0066 which includes code samples. Standard operation is described here with a 20.48MHz crystal. Example: 0xD8 0xA7 0x6A 0xD8 0xA8 0x50 0xD8 0xA9 0x00 wait 500s minimum 0xD8 0xA9 0x20 0xD8 0xA2 0x00 0xD8 0xBA 0x43 0xD8 0xB9 0xB2 ; PLL comparison frequency and input divider ; set PLL feedback divider ; power up the PLL ; PLL settling time ; enable PLL output ; clear hard reset ; enable clocking from the crystal ; power down ADC_Q Signal IF Frequency The ADC input IF frequency is programed via the ITB_FREQ_1, 2 registers. These make up a 14-bit value - ITB frequency (IF-To-Baseband). This value is calculated using the following formula: - 1 x F IF ITBFREQ = -------------------- x 16384 F ADC If the IF is being undersampled (as will be the case with a High IF signal input) then FIF is the subsampled IF, thus for a 36.1667MHz IF a derived value of 4.79MHz should be used in the equation (2 x 20.480MHz - 36.1667MHz = 4.79MHz): IF mode Low High High High High High IF [MHz] 4.57 36.00 36.125 36.1667 36.1667 36.00 0x0C 0x0D FIF [MHz] 4.57 4.96 4.835 4.7933 4.8333 5.00 0x05 0x31 FADC [MHz] 20.48 20.48 20.48 20.48 20.50 20.50 ITBFREQ -3657 (31B7h) -3968 (3080h) -3868 (30E4h) -3835 (3105h) -3863 (30E9h) -3996 (3064h) Example: 0xD8 0xD8 ; write ITBFREQ in two bytes for ; 36.1667MHz IF and 20.48MHz clock It is important that the ITB frequency should be calculated using the correct ADC clock frequency. Note) The spectrum invert bit in register ITB_CTL 0x0B may need to be set for Low IF operation, this may also depend upon the tuner. - 19 - CXD1968AR Channel Bandwidth The channel bandwidth is set indirectly by programming the TRL_NOMINALRATE_0, 1, 2 registers. TRLNOMINALRATE has changed from a 16-bit number on the CXD1976R to a 24-bit number on the CXD1968AR. These registers set the nominal rate of the sample timing NCO. TRL nominal rate is the ratio of the FFT time sample clock to the (fixed) ADC clock frequency. The following formula should be used to determine the TRLNOMINALRATE value: 16 x ChanBW 24 TRLNOMINALRATE = ------------------------------------- x ( 2 ) F ADC x 7 Note that the maximum allowable value of this register is 16777215 and the minimum is 11184811. Some common settings are given below, calculated for 20.48MHz and 20.5MHz clocks: Channel bandwidth 8MHz 7MHz 6MHz FADC = 20.48MHz 14979657 (E49249h) 13107200 (C80000h) 11234743 (AB6DB7h) FADC = 20.5MHz 14965043 (E45933h) 13094412 (C7CE0Ch) 11223782 (AB42E6h) Example: 0xD8 0x65 0x49 ; write TRL_NOMINALRATE in three bytes 0xD8 0x1B 0x92 ; for 8MHz RF channel 0xD8 0x1C 0xE4 ; and 20.480MHz clock Note) Error in the calculation of TRLNOMINALRATE more than 50ppm may compromise acquisition of 8K transmissions. Using Other IF Input Frequencies IF signals outside the range 4.50MHz to 4.57MHz and 36.000MHz to 36.1667MHz are not recommended. IF AGC Sense The IF AGC sense is programed by setting the AGC_neg bit in the AGC_CTL register. When set the AGC level output decreases when a larger signal is required, otherwise the AGC level output increases when a larger signal is required. Most tuners will not require this bit setting, so the register may not need to be programed. Spectrum Inversion The spectrum can be inverted to allow a reversed frequency spectrum from the tuner by setting the ITB invert spectrum bit in the ITB_CTL register. This may be required for operation with dual-conversion and Low IF architecture tuners. - 20 - CXD1968AR Forward Error Corrector Configuration Operation of the FEC block can be optimized by overriding some of the default register values. The following should be configured: Viterbi auto-reset Sync detect TS output mode Viterbi Block The disable bit in the AUTO_RESET register should be reset to optimize acquisition (the default value does not give optimum performance). Example: 0xD8 FEC Block 0xB1 0x00 ; enable Viterbi auto-reset The SET_SYNC_DETECT register should be set to 0x67 for optimum performance (the default value of 0xD6 does not give optimum performance). Example: 0xD8 0x86 0x67 ; set sync detect Transport Stream Outputs Also, in order to obtain a watchable picture after TS lock, the transport stream outputs must be enabled (normally these are tri-stated on power-up) by clearing bit 1 of FEC_PARAMS register. The following lines enable the most commonly used parallel TS output format: Example: 0xD8 0xD8 0x80 0x81 0x18 0xF4 ; enable parallel mode ; preferred TS configuration - 21 - CXD1968AR COFDM Signal Acquisition There are three stages in acquiring and locking to a COFDM signal. First, the COFDM demodulator must acquire the signal; then the FEC must synchronize to the Viterbi decoder output; finally, the FEC must synchronize to the transport stream. The CXD1968AR contains a new auto-recover algorithm. This is a hardware implementation which automatically reacquires an interrupted signal without intervention from the host controller. After the initial setup this minimizes the load on the host processor. The recommended method of operating the demodulator is to; 1. Configure the clocks and registers as described in the application note EAN-0066 and explained above. 2. Enable the core which will result in an acquired channel if present. 3. Set the auto-recover enable bit for automatic acquisition on any channel change. This uses the default acquisition mode and will acquire the channel regardless of the DVB-T mode. Default Acquisition In this mode, nothing need be known about the transmission parameters (except the channel bandwidth). The COFDM demodulator tries all the guard intervals in the two modes (2K and 8K) and then waits until it has received a whole super-frame before decoding the TPS data and configuring itself to receive that particular COFDM signal. Signaled TPS data in the stream is valid for the NEXT super-frame so the decoder may have to wait for 5 frames - 1 symbol (= 339 symbols) before it can use the received transmission parameters. Typical acquisition times for this mode: 125ms (2K) / 500ms (8K). Settings for Faster Acquisition There are several short cuts that can be taken to speed up acquisition. These depend on how the control registers are programed. It is not generally recommended that the user overrides the default settings unless the host processor has sufficient resources available. Transport Stream Locking FEC lock occurs at the input of the Reed-Solomon decoder when the number of sync bytes (47h) measured exceeds a certain value in the SET_SYNC_DETECT register. Transport Stream (TS) lock occurs at the output of the Reed-Solomon decoder, and uses the same mechanism as FEC lock. The SET_SYNC_DETECT register can be used to adjust the criteria for gaining/losing lock. The higher the number of bytes required to gain lock, the harder it is to acquire lock, but, once acquired, the chip should be less likely to lose lock. Lock can be lost either by counting the number of missed sync bytes (Decrement mode) or one missed sync byte can lose lock straight away (Reset mode). Reset and decrement modes are independently settable for TS lock and FEC lock. Example: 0xD8 Reacquisition 0x86 0x67 ; recommended configuration It may be necessary to reacquire a COFDM signal, for example if the user were to select a different RF channel, because of reception problems with a poorly sited set-top aerial or to simplify channel scanning. It is recommended to use the auto-recovery algorithm and default acquisition settings to minimize host processor overhead. The auto-recovery block has two modes of operation, scanning and zapping. Scanning mode will tell the auto-recovery state machine to attempt only 1 acquisition when enabled, after which it falls back to an idle state. The status can read by the host processor, ie. TPS and/or TS lock at the end of acquisition. Note that ready bits will indicate if the status readings are valid, ie. the process has completed. Zapping or channel change mode, also to be used during static operation to automatically recover a lost signal. In this mode the auto-recovery state machine will continuously monitor the demodulator status and reacquire when TPS/TS lock is lost. It is not necessary to read the status as it will continue to operate until disabled. - 22 - CXD1968AR Transport Stream Outputs Transport stream data is output on the TSDATA outputs; it is clocked by the TSCLK output. The TSSYNC output is active during the first byte of a TS packet. The TSVALID output can be used to indicate valid data. The TSERR output indicates a TS packet containing uncorrected errors. The TSLOCK output is set active high when a valid transport stream is locked on to. Enabling/Disabling the Transport Stream Output The transport stream outputs are enabled by setting the Tri_State_Outputs bit in the FEC_PARAMS register. Serial/Parallel Data Output Selection The default transport stream output mode is parallel. A serial output can be selected by resetting the TS_parallel_sel bit in the FEC_PARAMS register. Other Transport Stream Output Format Options The default output format is as below: In parallel mode, the MSB is output on the TSDATA7 pin, the LSB on TSDATA0. In serial mode, the MSB is output first and the LSB last all on TSDATA0. Data should be sampled on the rising edge of TSCLK. TSVALID, TSSYNC and TSERR are all active high. TSVALID active high indicates a valid data. TSERR is active for the first 188 bytes if that packet contains an uncorrected error. TSCLK is gated so that edges occur when TSVALID is active. The following options are available and can be selected by programming the FEC_PARAMS and BB_PARAMS registers: In parallel mode, the MSB can be output on TSDATA0 and the LSB on TSDATA7, and in serial mode the LSB can be output first and the MSB last by setting the Output_Sel_MSB bit in the FEC_PARAMS register. In serial mode, data can be output on TSDATA7 by setting the Ser_data-on_MSB bit in the FEC_PARAMS register. TSVALID, TSSYNC and TSERR can all be set active low by resetting the TSvalid_active_high, TSsync_active_high and TSerr_active_high bits respectively in the BB_PARAMS register. In parallel mode, the TSVALID output can be set to be active only during the first byte of a packet by setting the TSvalid_pulse bit in the BB_PARAMS register. TSERR can be set to be active only during the first byte (or bit in serial mode) by setting the TSerr_pulse bit in the BB_PARAMS register. If this bit is reset, then TSERR can be set to be active until the start of the next non errored TS packet by setting the TSerr_full bit in the BB_PARAMS register. TSCLK can be set to be active continuously by setting the TSclk_full bit in the BB_PARAMS register. - 23 - CXD1968AR Transport Stream Smoothing COFDM demodulation is naturally bursty. The demodulator operates on whole symbols of data at a time. A whole symbol must be stored before FFT processing can begin. Transformed data is read out of the FFT block as fast as possible into the following circuitry, resulting in a bursty TS. This bursty TS output can be smoothed by the on-chip TS smoothing buffer. The TS smoothing buffer is enabled by setting the ENABLE bit in the SMOOTH_CTRL register. The smoothing buffer can operate in an automatic or manual mode. Automatic Mode In automatic mode, the smoothing buffer applies the correct degree of smoothing for the COFDM signal being demodulated. Automatic mode is set by setting the DATA_PERIOD_AUTO bit in the SMOOTH_CTRL register. The channel bandwidth must also be programed into the SMOOTH_CTRL register using the CHANNEL_WIDTH bits. Example: 0xD8 Manual Mode 0xB4 0x03 ; enable automatic mode for 8MHz channel In manual mode, the degree of smoothing must be programed into the SMOOTH_DP1, 0 registers. The SMOOTH_DP0 register bits represent the fractional number of clock periods per TS word. A read from the SMOOTH_DP0 register returns the current value of the fractional part of the data period value. A read from SMOOTH_DP0 also causes the current value of the integer part of the data period value to be stored in a holding register, which can be accessed by reading from SMOOTH_DP1. For this reason it is recommended that SMOOTH_DP0 and SMOOTH_DP1 are read as a pair of registers, SMOOTH_DP0 first, followed by SMOOTH_DP1. Writing to SMOOTH_DP0 only has an effect when the DATA_PERIOD_AUTO bit of the SMOOTH_CTRL register is set to "0". In this case, writing to SMOOTH_DP0 has the effect of storing the 8-bit value in a holding register. Writing to SMOOTH_DP1 then has the effect of transferring data from the holding register to the SMOOTH_DP0 register proper. As with read accesses, it is recommended that write accesses to SMOOTH_DP0 and SMOOTH_DP1 are performed in pairs, SMOOTH_DP0 first, followed by SMOOTH_DP1. The SMOOTH_DP0 register bits represent the integer number of clock periods per TS word. A read from the SMOOTH_DP1 register returns the integer part of the data period value previously stored in a holding register when a read from the SMOOTH_DP0 register occurred (see SMOOTH_DP0 above). Writing to SMOOTH_DP1 only has an effect when the DATA_PERIOD_AUTO bit of the SMOOTH_CTRL register is set to "0". In this case, writing to SMOOTH_DP1 has the expected effect of updating the SMOOTH_DP1 register value, and has the additional effect of transferring data from a holding register (updated during a SMOOTH_DP0 write operation) into the SMOOTH_DP0 register (see SMOOTH_DP0 above). Monitoring the Smoothing Buffer Status The status of the smoothing buffer can be monitored by reading the SMOOTH_STAT register. The UNDERFLOW flag is set when an underflow condition has been detected. An underflow condition is where data is requested but cannot be provided because the read FIFO is empty. Note that when data is requested but cannot be provided because the next TS word is a sync and at the same time the SRAM FIFO does not contain a complete TS packet, this is part of the smoothing circuit's normal operation and is not classed as an underflow condition. Write a "1" to this bit location to clear this bit. Writing a "0" to this bit has no effect. The OVERFLOW flag is set when an overflow condition has been detected. Write a "1" to this bit location to clear this bit. Writing a "0" to this bit has no effect. Example: 0xD8 0xB5 0x03 ; to clear smoothing buffer status flags - 24 - CXD1968AR AGC There are two AGC outputs from the CXD1968AR - one for the RF tuner stages and one for the IF tuner stages. These generate PWM outputs that need to be integrated off-chip to provide an analog control signal to drive an external variable gain amplifier (analog VGA) in the tuner. Each integrator is implemented with a simple external single pole RC filter, values selected to give a cutoff frequency of 400Hz, removing the high frequency components. RF AGC The RF AGC outputs a PWM value via the RF AGC pin, which has been programed into the RF_IFAGC_CTRL0 and RF_IFAGCQ_PWM registers (renamed to cover the new ZIF AGC modes). The RF AGC pin is enabled by setting the RF_AGC_EN bit in the RF_AGC_CTRL0 register. The RF AGC pin may alternatively be used as a logic I/O pin, see below. IF AGC The IF AGC outputs a PWM value via the IF AGC pin. The AGC setting can be generated automatically or manually overridden. Automatic Gain Control The CXD1968AR contains an internal AGC block, which monitors the signal level at the output of the ADC and provides a Pulse Width Modulated (PWM) control signal to implement an automatic gain control loop. The AGC is capable of tracking out 60Hz AM interference with the specified time constant, and large changes in input level. A 40dB input swing can be corrected in 20ms (irrespective of QAM/ QPSK modulation scheme). The IF AGC automatic mode is enabled by resetting the AGC Set bit in the AGC_CTL register. The sense of the output is controlled by the AGC Neg bit in the same register. Manual Gain Control The AGC loop can be set manually using the AGC Set bit in the AGC_CTL register and entering a value of 0 to 1023 in the AGC Manual field in this register. RF AGC GPO The RF AGC pin may be configured to generate a fixed logic "0" or "1" output level (3.3V) where the RF AGC variable output function is not required. A typical application is to switch a dual bandwidth SAW filter or other circuit function in software. If the RF AGC output pin is to be used for this kind of application, the integrating RC filter is not required. This example generates a logic "1" or 3.3V level at this output. Example: 0xD8 0xB2 0x07 RF AGC GPI ; set RF AGC output pin High The RF AGC pin may be configured as a logic input (3.3V logic but 5V tolerant) where the RF AGC variable output function is not required. This may be used to sense operation of an external circuit. - 25 - CXD1968AR Monitoring Status Monitoring Transport Stream Lock This flag indicates that a valid MPEG2 transport stream is available at the CXD1968AR TSDATA outputs. Transport stream lock can be determined from reading the FEC_STATUS register, or from the INTERRUPT_SOURCE register. This bit is set in both registers whenever the Reed-Solomon FEC block has locked and a valid MPEG2 transport stream is now ready for output. Should the transport stream lose lock, then a TS lost lock flag bit is set in the FEC_PARAMS and INTERRUPT_SOURCE registers. FEC Lock FEC lock indicates that the Reed-Solomon FEC block has a coded MPEG2 transport stream at its input, which it is trying to decode. FEC lock can be determined from reading the FEC_STATUS register. AGC Lock The AGC lock flag in the COR_STAT register can be used to check that the input signal level is not varying and is not too high or too low (a high-level signal will cause distortion problems, and a low-level signal will suffer from quantization noise). Core State Machine The COFDM demodulator contains a state machine, which can be used to gain information as to why the CXD1968AR has not locked on to an incoming OFDM signal. The core has the following states: 0000 0001 0010 0011 0100 0101 0110 State 0: IDLE State 1: WAIT_ TRL State 2: WAIT_AGC State 3: WAIT_SYR State 4: WAIT_PPM State 5: WAIT_TPS State machine not forced WAIT_TRL WAIT_AGC WAIT_SYR WAIT_PPM WAIT_TPS MONITOR _TPS Core is disabled. Core is calculating a value to be used later. Core is waiting for input signal levels to stabilize to an acceptable value before attempting to demodulate the incoming signal. AGC has locked, waiting for the core to determine the guard interval and its position. Waiting for the pilot processing module to find the pilot carriers. Waiting for the core's TPS decoder to acquire frame sync (which determines the symbol number). State 6: MONITOR_TPS Signal ready to be fed to the Viterbi decoder, continue to monitor the TPS data for parameter changes. - 26 - CXD1968AR Performance Monitoring Pre-Viterbi BER Pre-Viterbi BER readings are available from the VIT_BER register. The sampling period is adjustable in the VIT_CTRL register. Reed-Solomon BER Pre- or Post-Reed-Solomon BER can be either measured or estimated using the BER_ESTIMATE register. In measurement mode, NULL packets must be used. In estimate mode, any data can be used. Estimation mode assumes that all post Viterbi errors are corrected by the Reed-Solomon decoder. Measurement mode is selected by setting the Measurement_Sel bit in the FEC_PARAMS register. Readings should be taken whenever the NEW_BER bit is set. If too many errors have been recorded during the specified measurement period, then the BERCNT_Overflow bit will be set. Should this occur, the reading should be discarded and a lower measurement period selected. The measurement period is set using the BER_PERIOD register. Uncorrected Errors Errored Second This indicates that the Reed-Solomon FEC block could not correct all the errors found in one or more 204-byte packets received during the last second. This is because >8 errors were found in the packet. Errored second can be determined from reading the FEC_STATUS register, or from the INTERRUPT_SOURCE register. Severely Errored Second This indicates that the Reed-Solomon FEC block has been unable to correct the errors found in N or more 204-byte packets received during the last second. This is because >8 errors were found in each of the packets. N is set using the LT_QLTY_THRESHOLD register. Typically, this can be used to set a threshold value with regard to picture degradation, depending on the quality of service required. Severely errored second can be determined from reading the FEC_STATUS register, or from the INTERRUPT_SOURCE register. Codeword Reject Count This indicates the number of rejected codewords (MPEG-2 packets) in one second. This is recognized to be a particularly useful measurement as it is more closely aligned to receiver picture failure than BER. Signal-to-Noise Estimate The CHC_SNR register can be used to obtain an estimate of the signal-to-noise ratio of the received signal either for each carrier individually or as a mean across the channel. If the mean bit in the SNR_CARRIER_2 register is set, then a mean value across the channel can be read from the CHC_SNR register. If the mean bit in the SNR_CARRIER_2 register is reset then the carrier number can be selected by programming the SNR carrier number bits in the SNR_CARRIER_1, 2 registers and after at most one symbol the SNR for that carrier can be read from the CHC_SNR register (the host controller must wait for one symbol to be sure that the data is ready). A higher value indicates a lower operating SNR. The estimated value is independent of the channel response, and accurate to about 1dB. The value in this register (N) can be converted to an approximate dB value using the following empirical formula: CHC_SNR SNR [ dB ] = -----------------------------8 - 27 - CXD1968AR Interrupts These can be used to quickly ascertain the status of the chip. This can be done in one of two ways: 1. Regularly polling the interrupt flags over the I2C bus. 2. Using the INT pin to raise a hardware interrupt, then getting the host controller to read the interrupt flags to determine the type of interrupt. The interrupts are of two basic types: 1. High-level interrupts: the flags for these are contained in the interrupt status register (INTERRUPT_SOURCE). 2. OFDM core interrupts: the flags for these are contained in the core interrupt status register (COR_INTSTAT). High-level Interrupts These interrupts relate to the key stages in acquiring transport stream lock. Interrupt flags are available for the following events: 0. COFDM demodulator interrupt (poll the COR_INTSTAT register to find out why) 1. Transport stream lock 2. Transport stream lost lock 3. Reserved 4. Errored second detected 5. Severely errored second detected 6. Codeword rejected (>8 errors in current packet) 7. Transport stream smoothing under/over flow To clear each interrupt, write a "1" to the corresponding bit in the INTERRUPT_SOURCE register after the interrupt has occurred. COFDM Demodulator Interrupts COFDM demodulator interrupt flags are available for the following events: 0. AGC lock change (AGC gained lock/AGC lost lock) 1. End of symbol (from Symbol Recovery block) 2. FFT done: FFT processing complete on current symbol 3. Receipt of a TPS block 4. Change of TPS parameters 5. TPS block has a bad BCH checksum. Enabling Core Interrupts Interrupts are enabled using the COR_INTEN register. To enable any core interrupt, the INTEN Global bit in the COR_INTEN register must be set. Each individual interrupt is then enabled by setting the appropriate bit in the COR_INTEN register. - 28 - CXD1968AR Energy Saving Modes Low-power Standby Mode This mode reduces the nominal power consumption of the CXD1968AR in IF mode from 140mW to 10mW. To obtain maximum benefit it is necessary in software to; Disable PLL and stop internal clocks Power-down the ADC Recovery from low-power standby mode can be achieved by cold reset to all blocks. Example: 0xD8 0xA9 0x41 ; power-down PLL and stop clock 0xD8 0xB9 0x01 ; power-down ADC Ultra Low-power Shutdown Mode This mode reduces the nominal power consumption of the CXD1968AR in IF mode from 140mW to < 1mW. This mode is entered through external control of OSCEN (Pin 40). Grounding this pin will stop the crystal oscillator and all on-chip activity. The CXD1968AR should be reset when resuming from shutdown mode. - 29 - CXD1968AR 4. Application Circuit GND C16 33pF R5 100 Y2 20.480MHz R6 2.2M C35 33pF 1.2V-AD 1.2V-D GND 3.3V-D 1.2V-D 3.3V-D GND R1 10k GNDGND GNDGND R2 10k 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XTALI A0 TESTMODE PADVSS DIVSS XVSS CVSS XTALO OSCEN DVSS PADVDD TRSTN DIVDD XVDD CVDD DVDD GND 49 AINP_Q 50 AINM_Q 3.3V-A GND GND C31 100nF C69 1nF TUNER_IF_NEG C71 1nF TUNER_IF_POS GND 3.3V-A GND 51 AVDD_Q 52 AVSS_Q 53 GUARD_Q 54 DAREFP 55 DAREFM 56 GUARD_I 57 AINM_I 58 AINP_I 59 AVSS_I 60 AVDD_I 61 REFIN 62 REFOUT TMS 32 TDI 31 TDO 30 TCLK 29 CVSS 28 CVDD 27 SDA 26 SCL 25 DVDD 24 DVSS 23 3.3V-D GND GND 1.2V-D SDA SCL R13 2.2k R14 2.2k 3.3V-D TSDATA7 22 TSDATA6 21 TSDATA5 20 TSDATA4 19 RF_IFAGC_Q TSDATA3 18 TSDATA0 TSDATA1 INTRPTN TSVALID RESETN TSSYNC IFAGC_I TSDATA2 17 CVDD CVSS GND 1.2V-D TSERR TSCLK TUNER_DAT TUNER_CLK R19 10k R20 10k 63 TUNERDAT 64 TUNERCLK CVDD 1 5V-A TUNER_IF_AGC C33 470nF GND Mount components close to Pin 2 R23 1.0k 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND 1.2V-D GND 3.3V-D DVDD CVSS DVSS TSData[0:7] 3V-VCC TSCLK TSVALID Power supply decoupling. All supply pins to be decoupled with 100nF ceramic capacitors. (not shown) R16 10k R17 10k TSSYNC TSERROR RESETN C36 100nF GND INTRPTN Note) For High IF or Low IF mode, use PIN 57, 58 (AINM_I, AINP_I) as the ADC input. And, PIN 49, 50, which are unused, should be kept open. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Fig. 5. Application and Test Measurement Schematic for IF Mode of Operation - 30 - CXD1968AR 5. Design Guidelines This section describes the application of the CXD1968AR DVB-T COFDM demodulator IC. The schematic contained within the previous section should be used to assist with following descriptions. Refer to the separate engineering application notes for additional information about specific configurations and uses. EAN-0065 is intended to assist users familiar with the CXD1976R in making the transition to the CXD1968AR. Circuit Configurations The CXD1968AR has the capability to operate with High IF, Low IF and Zero IF conventional or silicon tuners. The application described in this section is for a conventional High IF tuner. ADC Input The ADC input of the CXD1968AR is directly compatible with differential sources. Where the tuner can supply only a single-ended IF signal, a balun is recommended to maximize the dynamic range of the IF strip. The ADC input has a high impedance input (> 1k). The tuner output impedance is normally low (< 100) and it is not necessary to match to the ADC. The differential inputs are self-biasing and our recommendation is to AC couple the input signals with 1nF or larger capacitors. Note) For High IF or Low IF mode, use PIN 57, 58 (AINM_I, AINP_I) as the ADC input. ADC Reference Components The ADC reference voltage at Pins 61 and 62 (connected together) should be decoupled with 100nF multilayer capacitor for optimum performance. AGC The CXD1968AR generates an IF AGC output. This signal is a digital PWM format requiring an integrating RC filter to provide a variable DC control voltage for the tuner or IF circuit. A second AGC output can be generated for RF gain control. The output signal is also PWM format, but may be configured as a fixed logic level output for general-purpose control functions. When used as an AGC output, an integrating RC filter is required. This pin may alternatively be used as a logic input at a nominal 3.3V but is 5V compliant. The application values for the PWM integrating filter of 1000 and 470nF are chosen to give a 0.5ms time constant which approximates to a 400Hz cutoff frequency. For the IF AGC loop, this value is chosen as a compromise between suppressing the PWM high-frequency components and permitting the AGC loop to track 50/60Hz AM interference which may be present on the received signal. Typically the AGC response time to a step input, as might occur changing channel, is 20ms. If the filter values are modified perhaps to achieve faster channel acquisition, then note the possible impact on AM rejection. Clock and Crystal Oscillator The oscillator cell will operate with an external crystal or use an external clock, this is configured at startup by register settings described in the application note EAN-0066. If using an external clock, this must be present before programming can be applied. Performance with an external clock may be compromised if the quality of the reference signal is poor. - 31 - CXD1968AR JTAG The JTAG facility can be utilized, but refer to section 2 of this datasheet for information on how to configure the connections. It may be necessary to apply pull-down resistors to these pins: TCK TRSTN Pin 29 Pin 34 Power Supply Sequencing During the power-up sequence of the 1.2V and 3.3V supplies, it is important to ensure that the 1.2V supply is not applied before the 3.3V supply. Failure to do this could result in latch up and the CXD1968AR will not function correctly. During power-down the 3.3V supply should not fall below the 1.2V supply, as both decay. Both conditions can be met by deriving the 1.2V supply from the 3.3V supply. If this configuration is not utilized or the timing cannot be guaranteed, it is possible to prevent supply latchup by adding a Schottcky diode between the supplies. Connect the diode with anode to 1.2V supply and cathode to 3.3V supply. This is only appropriate when both analog and digital 3.3V supplies are derived from the same regulator. The diode used must be a Schottcky type for low forward voltage drop, ie. 0.4V or less. This solution is applicable to both power-up and power-down conditions. Reset Note the hardware reset requirements outlined in section 3. As has been stated, when the CXD1968AR is powered up, it must be hard reset. This can be achieved simply by using an external RC circuit with time constant of around 1ms, values of 10k and 100nF are employed in the recommended application. Alternatively this function may be provided by a specific device or host controller and the timing will be dependant upon supply rise time. Pull-ups The following pins should be used with pull-up resistors: SDA SCL QSDA QSCLK INTRPTN Pin 26 Pin 25 Pin 63 Pin 64 Pin 5 (if used) A nominal value of 10k is used with the CXD1968AR but other values are permissible dependant upon the interface requirement. The maximum loading is stated in the DC Electrical Characteristics, a value of less than 1000 is not advisable. - 32 - CXD1968AR Printed Board Layout Board layout recommendation for CXD1968AR. Supply and Ground The CXD1968AR uses three supplies: 1.2V digital 3.3V digital 3.3V analog for core processing for clock and I/O for ADC All supplies should be decoupled close to the supply pins. A single ground plane is recommended. However in some situations a split analog/digital ground plane can offer improved immunity from digital noise. Which option yields better performance will depend upon the application, ie. location of supplies and interference sources. These rules should be adhered to, minimizing the risk of performance degradation: The supplies may be tracked-in (2-layer board) or assigned to a specific power-plane (multilayer). With either form it is essential to provide a low-impedance ground return to the source of the supply. A continuous ground plane is preferred as a starting point. The quiet analog section resides at one corner of the device, Pins 47 to 62. The supply to this section should feed into and return (via ground) without crossing over the digital section of board. The digital section should avoid a ground return path through the analog section. Failure to ensure this may compromise performance of the demodulator. If it is not possible to ensure uninterrupted ground return paths back to each supply source, it may be necessary to partition the ground plane to force digital supply ground return currents to avoid the analog section. It is also advisable to link analog and digital grounds in the area directly below the CXD1968AR. ESD Other constraints include immunity from ESD. The instantaneous energy presented by any electrical impulse should avoid passing close to or through the CXD1968AR. Similarly any connection to the CXD1968AR should not be susceptible to or protected against ESD pickup. For circuit connections that may travel outside of the immediate vicinity around the CXD1968AR, it is recommended that low-value series resistors are employed to limit charge transfer. A typical value would be 47 to 100. ADC Input The signal connections to the ADC input should be of similar length and routed together. Failure to do so may compromise the common mode rejection properties of the differential input circuit. Low-impedance drive to the ADC will minimize the risk of spurious pickup. The connection between tuner IF output and the CXD1968AR ADC input should be routed over continuous analog ground plane. ADC Reference Components As for the ADC input connection, the capacitor between DAREFP and DAREFM should be positioned above continuous analog ground plane. AGC The AGC PWM integrating RC filter (either IF or RF when used) should be positioned as close to the CXD1968AR as practical, ideally within 5mm. The pinout of the CXD1968AR has been improved to assist this constraint. It will prevent harmonics of the PWM signal breaking through into the IF circuit. The PWM edges are slew-rate limited but good practice will ensure no interference with the IF input. - 33 - CXD1968AR Crystal Oscillator When used with an external clock signal, a level of 1Vp-p is recommended. This should be AC coupled, 1nF minimum. The oscillator cell will operate as a buffer but requires the 2.2M feedback resistor, as present for the crystal, to provide a DC path for the self-biasing action. Transport Stream The transport stream data rate is relatively low for smoothed parallel mode of operation, but is clocked at 40MHz in serial mode. In this mode the logic edges could create significant reflection in unterminated long printed-board tracks. It is recommended that source resistors are used at the CXD1968AR prior to launching along tracks of 50mm or more. A suitable source resistor value of 39 to 47 should be considered. - 34 - CXD1968AR 6. Electrical Characteristics Absolute Maximum Ratings (Ta = 25C, AVSS = 0V, DVSS = 0V, CVSS = 0V) Item Digital power supply (I/O) Analog power supply (ADC) Digital power supply (Core) Input voltage Output voltage Analog voltage Operating temperature Storage temperature Symbol DVDD AVDD CVDD Vin Vout Vina Topr Tstg DAREFN, DAREFP, REFIN, VCM, REXT_I, REXT_Q, AINM_I, AINP_I, AINM_Q, AINP_Q Condition Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -40 -65 Max. +4.6 +4.6 +1.68 +4.6 +4.6 +4.6 +125 +150 Unit V V V V V V C C Note) 1. The device must be operated within the limits of the absolute maximum ratings. If the device is operated outside these conditions, the device may be permanently damaged. 2. Functional operation at or outside any of the conditions indicated in the absolute maximum ratings is not implied. 3. Exposure of the device to the absolute maximum rating condition for extended periods can affect system reliability. 4. 5V tolerant inputs are only 5V tolerant while the device power is applied. If no device power is applied there in no protection to 5V levels and the device may be permanently damaged. It is important to observe the conditions for 5V protection when sequencing power supplies in the application. 5. Refer to section 5, Design Guidelines, regarding power-up/down sequencing. The core (1.2V) should not be powered-up when the I/O (3.3V) is powered-down. Recommended Operating Conditions Item Digital power supply (I/O) Analog power supply Digital power supply (Core) DC input voltage DC input voltage Symbol DVDD AVDD CVDD VIH VIL Pins RF_AGC_Q, IFAGC_I, TUNERDAT, TUNERCLK, TSVALID, TSERR, TSDATA[7:0], TSSYNC Pins TDO, INTRPTN, TSCLK, SCL, SDA Operating frequency (Internal Xtal oscillator) Operating frequency (External 4-20MHz reference) Ambient temperature Fop Fop Ta 0 20.48 20.50 +70 DVSS = 0 AVSS = 0 CVSS = 0 Condition Min. 3.0 3.0 1.08 2 -0.3 Typ. 3.3 3.3 1.2 Max. 3.6 3.6 1.32 5.5 0.8 8.0 Unit V V V V V mA High-level and Low-level output current IOH, IOL 12 mA MHz MHz C - 35 - CXD1968AR DC Electrical Characteristics (0C < Ta < 70C, AVSS = 0V, DVSS = 0V, CVSS = 0V, 3.0V AVDD 3.6V, 3.0V DVDD 3.6V, 1.08V CVDD 1.32V) Item Input Low voltage Input High voltage Input Low current Input pull-up resistor Input High current Input pull-down resistor Symbol VIL VIH IIL RPU IIH RPD IOL = 8mA, Pins RF_AGC_Q, IFAGC_I, TUNERDAT, TUNERCLK, TSVALID, TSERR, TSDATA[7:0], TSSYNC IOL = 12mA, Pins TDO, INTRPTN, TSCLK, SCL, SDA IOL = 8mA, Pins RF_AGC_Q, IFAGC_I, TUNERDAT, TUNERCLK, TSVALID, TSERR, TSDATA[7:0], TSSYNC IOL = 12mA, Pins TDO, INTRPTN, TSCLK, SCL, SDA Supply current (IF mode) Supply current (ZIF mode) ADC input dynamic range Common mode output IDD3.3 IDD1.2 IDD3.3 IDD1.2 VAIN VCM Differential signal Current with TS outputs enabled Current with TS outputs enabled 24 50 40 50 0.7, 1.0, 1.5, 2.0 1.25 mA mA mA mA Vp-p V 45 93 Condition Min. -0.3 2 -10 39 55 85 10 198 Typ. Max. 0.8 5.5 Unit V V A k A k Output voltage Low VOL 0.4 V Output voltage High VOH 2.4 V Note) Electrical characteristics measured with 50pF load. - 36 - CXD1968AR AC Electrical Characteristics Transport Stream Interface tCLKPW tCLKJIT TSCLK TSDATA[7:0], TSSYNC, TSVALID, TSERR tSETUP tHOLD Fig. 6. Transport Stream Timing Diagram Conditions Temperature: 0C < Ta < 70C Voltage: 3.15V AVDD 3.45V, 3.15V DVDD 3.45V, 1.08V CVDD 1.32V Parallel Mode - Smoothing Off Item Transport stream setup time Transport stream hold time TSCLK frequency TSCLK width TSCLK jitter tCLKPW tCLKJIT Symbol tSETUP tHOLD Min. 39 45 10.25 48 1 Typ. Max. 45 49 Unit ns ns MHz ns ns Parallel Mode - Smoothing On Item Transport stream setup time Transport stream hold time TSCLK frequency TSCLK width TSCLK jitter tCLKPW tCLKJIT Symbol tSETUP tHOLD Min. 120 125 0.68 44 24.8 Typ. Max. 728 708 3.7 Unit ns ns MHz ns ns - 37 - CXD1968AR Serial Mode - Smoothing Off Item Transport stream setup time Transport stream hold time TSCLK frequency TSCLK width TSCLK jitter tCLKPW tCLKJIT Symbol tSETUP tHOLD Min. 3 3.8 81.96 5.5 1 Typ. Max. 4.6 5 Unit ns ns MHz ns ns Serial Mode - Smoothing On Item Transport stream setup time Transport stream hold time TSCLK frequency TSCLK width TSCLK jitter tCLKPW tCLKJIT Symbol tSETUP tHOLD Min. 9 12 41.67 12 1 Typ. Max. 12 15 Unit ns ns MHz ns ns Note) Dependent upon code-rate and modulation. - 38 - CXD1968AR Transport Stream Interface (Serial Mode) (0C < Ta < 70C, AVSS = 0V, DVSS = 0V, CVSS = 0V, 3.15V AVDD 3.45V, 3.15V DVDD 3.45V, 1.08V CVDD 1.32V) Item tTSLOCK, Transport stream locked to valid TSSYNC, TSVALID and TSERR tTSJIT(E), Transport stream clock jitter (smoothing enabled) tTSSU, Transport stream TSDATA, TSSYNC, TSVALID and TSERR setup time to TSCLK active edge tTSPW(E), Transport stream TSCLK pulse width (smoothing enabled) fTSCLK(E), Transport stream TSCLK frequency (smoothing enabled) tTSHD, Transport stream TSDATA, TSSYNC, TSVALID and TSERR hold time from TSCLK active edge (5) 3 Symbol (1) (2) (3) 6 Condition Min. 146 1 Typ. Max. Unit ns ns ns (4) 12.2 ns 41 MHz ns Note) The items in the above table are applicable only if transport stream smoothing is enabled. Use of the serial transport stream output interface with transport stream smoothing disabled is not recommended. (4) TSCLK (3) (2) TSDATA(7)/(0) (5) TSSYNC TSVALID, TSERR Lock Transport Stream Locked (1) Tranport Stream Interface (Serial Mode) - 39 - CXD1968AR I2C Interface SDA (17) (18) SCL P S (18) (19) (22) (20) (23) (21) Sr (24) P (0C < Ta < 70C, AVSS = 0V, DVSS = 0V, CVSS = 0V, 3.15V AVDD 3.45V, 3.15V DVDD 3.45V, 3.15V CVDD 3.45V) Item fSCL, SCL clock frequency tSDABUF, Bus free time between a STOP(P) and START(S) condition tSTAHD, Hold time (repeated) START condition. After this period, the first clock pulse is generated. tSCLLOW, Low period of SCL clock tSCLHIGH, High period of SCL clock tSTASU, Setup time for a repeated START condition tSDAHD, SDA data hold time tSDASU, SDA data setup time tSTOSU, Setup time for STOP condition Symbol (16) (17) Condition Min. 0 1.3 Typ. Max. 400 Unit kHz s (18) 0.6 s (19) (20) (21) (22) (23) (24) 1.3 0.6 0.6 0 100 0.6 0.9 s s s s ns s - 40 - CXD1968AR 7. Package Pin Layout PADVDD (1.2V alog) PADVSS (0V alog) DIVDD (1.2V alog) XVDD (3.3V xtal) CVDD (1.2V dig) XVSS (0V xtal) DVDD (3.3V dig) DIVSS (0V alog) CVSS (0V dig) DVSS (0V dig) OSCEN XTALO 48 AINP_Q 49 AINM_Q 50 AVDD_Q (3.3V alog) 51 AVSS_Q (0V alog) 52 GUARD_Q 53 DAREFP 54 DAREFM 55 GUARD_I 56 47 46 45 44 43 42 41 40 39 38 37 36 35 34 TRSTN XTALI 33 32 TMS 31 TDI 30 TDO 29 TCLK 28 CVSS (0V dig) 27 CVDD (1.2V dig) 26 SDA 25 SCL CXD1968AR AINM_I 57 AINP_I 58 AVSS_I (0V alog) 59 AVDD_I (3.3V alog) 60 REFIN 61 REFOUT 62 TUNERDAT 63 TUNERCLK 64 1 RF_IFAGC_Q 2 IFAGC_I 3 CVSS (0V dig) 4 CVDD (1.2V dig) 5 INTRPTN 6 RESETN 7 TSERR 8 TSSYNC 9 TSVALID 10 TSCLK 11 DVSS (0V dig) 12 DVDD (3.3V dig) 13 TSDATA0 14 TSDATA1 15 CVDD (1.2V dig) 16 CVSS (0V dig) 24 DVDD (3.3V dig) 23 DVSS (0V dig) 22 TSDATA7 21 TSDATA6 20 TSDATA5 19 TSDATA4 18 TSDATA3 17 TSDATA2 Fig. 7. CXD1968AR Pinout - 41 - TESTMODE A0 CXD1968AR 8. Pin Description Pin No. 43 42 40 6 Symbol Type Drive Function Clock and Reset XTALO XTALI OSCEN RESETN Output Input Input Input 5V tolerant Schmitt trigger N/A N/A N/A N/A Crystal oscillator cell output. Crystal oscillator cell input and input for 4-20MHz tuner clock reference. Crystal oscillator cell enable. Active low hardware reset. Dual ADC Interface 55 54 61 62 57 58 56 53 50 49 22 21 20 19 18 17 14 13 DAREFM DAREFP REFIN REFOUT AINM_I AINP_I GUARD_I GUARD_Q AINM_Q AINP_Q TSDATA7 TSDATA6 TSDATA5 TSDATA4 TSDATA3 TSDATA2 TSDATA1 TSDATA0 Analog output Analog output Analog input Analog input/ output Analog input Analog input Analog input Analog input Analog input Analog input N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Output pin to external 0.1F bypass capacitor for the ADC internal DAC lower reference voltage. Output pin to external 0.1F bypass capacitor for the ADC internal DAC upper reference voltage. Reference voltage input for the I channel ADC, normally left unconnected. Ground reference input for REFIN (Pin 52), normally left unconnected. Differential analog input (I channel ADC). Differential analog input (I channel ADC). Guard ring input for I channel ADC, this should be connected to analog AVSS_I via a low impedance trace. Guard ring input for Q channel ADC, this should be connected to analog AVSS_Q via a low impedance trace. Differential analog input (Q channel ADC). Differential analog input (Q channel ADC). MPEG2 Transport Stream Interface Tri-state output 5V tolerant slew rate limited[7:1] with pull-up 8mA MPEG2 transport stream parallel data output. If serial mode is selected data output is either TSDATA0 (Pin 13) or TSDATA7 (Pin 22). Tri-state following hardware reset. 9 TSVALID Tri-state output 5V tolerant slew rate limited output with pull-up 8mA Identifies data portion of transport stream packet (excludes parity bytes). The polarity and timing of this valid signal are programmable. Tri-state following hardware reset. MPEG2 transport stream byte clock. If serial MPEG2 transport stream is selected this output becomes the bit clock. The polarity of this clock is programmable. Tri-state following hardware reset. 10 TSCLK Tri-state output 5V tolerant 12mA - 42 - CXD1968AR Pin No. 8 Symbol Type Tri-state output 5V tolerant slew rate limited output with pull-up Tri-state output 5V tolerant slew rate limited output with pull-up Drive Function Indicates MPEG2 47h sync byte in transport stream packet. The polarity of this sync signal is programmable. Tri-state following hardware reset. MPEG2 transport stream error flag. Indicates uncorrectable errors in current packet. The polarity and timing of this error signal is programmable. Tri-state following hardware reset. TSSYNC 8mA 7 TSERR 8mA Host Control Interface 26 SDA Bi-directional 5V tolerant slew rate limited opendrain output Bi-directional 5V tolerant slew rate limited opendrain output Input 5V tolerant Output 5V tolerant opendrain slew rate limited output Output Slew rate limited Bi-directional 5V tolerant slew rate limited output with pull-up Bi-directional 5V tolerant opendrain output Bi-directional 5V tolerant opendrain output Input 5V tolerant with pull-down Input 5V tolerant with pull-up Tri-state output 5V tolerant 12mA I2C data. Must be pulled up by external resistor to 3.3V or 5V. Suggested value 10k. I2C clock. Must be pulled up by external resistor to 3.3V or 5V. Suggested value 10k. I2C address (variable part). Bit 0 of I2C device address. Connect to either DVDD or DVSS. Programmable interrupt pin. Must be pulled up by external resistor to 3.3V or 5V. Suggested value 10k. 25 SCL 12mA 35 A0 N/A 5 INTRPTN 12mA Tuner Interface (Control and AGC) 2 IFAGC_I 8mA IF AGC pulse width modulated (PWM) output for I channel ADC. Mode 1: RF AGC pulse width modulated (PWM) output (IF mode only) Mode 2: IF AGC pulse width modulated (PWM) output for Q channel ADC (ZIF mode) Mode 3: PLL locked status input, and general-purpose input (IF mode only) Mode 4: General-purpose digital output (IF mode only) Quiet I2C clock. Must be pulled up by external pull-up resistor to 3.3V or 5V if used. Suggested value 10k. Quiet I2C data. Must be pulled up by external pull-up resistor to 3.3V or 5V if used. Suggested value 10k. 1 RF_IFAGC_Q 8mA 64 TUNERCLK 8mA 63 TUNERDAT 8mA Testability and Evaluation Interface 33 TESTMODE N/A Normal Mode: Connect to DVSS. JTAG Test Mode: Set high to enable scan test or SRAM BIST modes. 34 30 TRSTN TDO N/A 12mA Normal Mode: Connect to DVSS. JTAG Test Mode: JTAG test reset input Normal Mode: Leave unconnected. JTAG Test Mode: JTAG test data output - 43 - CXD1968AR Pin No. 31 Symbol TDI Type Input 5V tolerant with pull-up Input 5V tolerant with pull-up Input 5V tolerant Digital I/O power supply Digital I/O power supply Digital core logic power supply Digital core logic power supply Digital power supply Digital power supply Drive N/A Function Normal Mode: Leave unconnected. JTAG Test Mode: JTAG test data input Normal Mode: Leave unconnected. JTAG Test Mode: JTAG test mode select Normal Mode: Connect to DVSS. JTAG Test Mode: JTAG test clock. Supplies digital I/O cell power. Connect to DVSS (0V). Supplies digital I/O cell power. Connect to DVDD (3.3V 10%). Supplies internal digital logic and SRAM power. Connect to DVSS (0V). Supplies internal digital logic and SRAM power. Connect to DVDD (1.2V 10%). Supplies ADC "clock divider" function only. Connect to clean supply DVSS (0V) for best ADC operation. Supplies ADC "clock divider" function only. Connect to clean supply DVDD (1.2V 10%) for best ADC operation. Supplies analog functions within PLL. No connection to other digital supplies within IC. For best performance connect to clean separate supply. Connect to DVSS (0V). Supplies analog functions within PLL. No connection to other digital supplies within IC. For best performance connect to clean separate supply. Connect to DVDD (1.2V 10%). Supplies ADC (I channel) functions and analog I/O power. Connect to clean AVSS (0V). Supplies ADC (I channel) functions and analog I/O power. Connect to clean AVDD (3.3V 10%). Supplies ADC (Q channel) functions and analog I/O power. Connect to clean AVSS (0V). Supplies ADC (Q channel) functions and analog I/O power. Connect to clean AVDD (3.3V 10%). Supplies crystal only. Connect to clean AVSS (0V). Supplies crystal only. Connect to clean AVDD (3.3V 10%). 32 29 TMS TCK N/A N/A Power Supplies 23, 11, 37 36, 24, 12 28, 16, 3, 38 39, 27, 15, 4 46 DVSS DVDD CVSS CVDD DIVSS 45 DIVDD 47 PADVSS PLL analog and digital supply 48 PADVDD PLL analog and digital supply Analog power supply Analog power supply Analog power supply Analog power supply Analog power supply Analog power supply 59 60 52 51 44 41 AVSS_I AVDD_I AVSS_Q AVDD_Q XVSS XVDD - 44 - CXD1968AR 9. Control Register Definitions Register Map Name Addr. R/W 7 6 5 4 3 2 1 0 CXD1968AR COFDM Core Registers COR_CTL COR_STAT 00 01 R/W R Reserved CHC Tracking INTEN Global TPS Locked Core Active SYR Locked Hold AGC Locked Core State[3:0] Core State[3:0] INTEN AGC INTEN TPS INTEN TPS INTEN TPS Lock RCVD RCVD RCVD Change BCHBad Changed Update INTSTAT AGC Lock Change Force INTSTAT TPS BadBCH Mode INTSTAT INTSTAT TPS RCVD TPS RCVD Changed Update Guard AGC Set COR_INTEN 02 R/W Reserved INTEN SYR INTEN FFT SymEnd Done INTSTAT SYR SymEnd INTSTAT FFT Done COR_INTSTAT COR_MODEGUARD AGC_CTL 03 04 05 06 07 08 09 R/W Reserved R/W ZIF Enable R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W TEST9[7] Reserved Reserved CCS Enable AGC After DCC Reserved Delay Startup[7:5] AGC Use AGC BW Reduction[1:0] AGC Neg Last Value AGC Manual[7:0] AGC_MANUAL AGC_TARGET Reserved AGC Target[7:0] AGC Gain I[7:0] Lock Q Lock I AGC Locked Reserved ITB Frequency[7:0] AGC Manual[11:8] AGC_GAIN 0A 0B 0C 0D 0E 0F 10 11 12 17 AGC Gain I[11:8] ITB Invert Spectrum ITB_CTL ITB_FREQ ITB Frequency[13:8] DAGC Disable DAGC BW Reduction[1:0] CCS Freq[7:0] CAS DAG Gain[7:0] TEST9[6:3] TEST5 Reserved SYR Locked Reserved TEST9[2] SYR Mode TEST9[1] TEST9[0] CCSMU[2:0] CAS_CTL CAS_FREQ CAS_DAGCGAIN TEST9 SYR_STAT FFT_CTL ACS Disable SYR Guard[1:0] FFT Test FFT Manual FFT Inverse Trigger Mode Transform Reserved PPM Reduced Search Time Enable SCR No Common Phase PPM Disable Find Scattered Pilots SCR Disable SCR_CTL 18 R/W Reserved SYR Adjust Decay[2:0] PPM_CTL 19 R/W Reserved PPMMaxFreq[2:0] Reserved PPM Bypass Corr TRL_CTL TRL_NOMINALRATE_1 TRL_NOMINALRATE_2 TRL_TIME 1A 1B 1C 1D 1E 1F 20 R/W R/W R/W R R R/W R R R Reserved TRL Track Gain Factor[3:0] TRL Nominal Rate[15:8] TRL Nominal Rate[23:16] TRL Timing Offset[7:0] TRL Timing Offset[15:8] TRL Loop Gain[2:0] CRL_CTL CRL Disable Fine CRL Track Gain Factor[3:0] CRL Frequency Offset[7:0] CRL Frequency Offset[15:8] CRL Loop Gain[2:0] CRL_FREQ 21 22 Sign Ext CRL Frequency Offset[22:16] - 45 - CXD1968AR Name CHC_CTL CHC_SNR BDI_CTL Addr. R/W 23 24 25 R/W R R/W 7 6 Mean Pilot Gain[2:0] 5 4 3 2 Disable Noise Normal 1 Disable CHC Predictor 0 CHC Interpolator Manual Disable Bad Mean Pilot Pilots CHC SNR[7:0] Reserved BDI LPSelect Reserved DMP Disable CSI Weight DMP_CTL 26 R/W TPS Changed TPS BCHOK Reserved TPS_RCVD_1 TPS_RCVD_2 TPS_RCVD_3 TPS_RCVD_4 TPS_RESERVED_1_ODD TPS_RESERVED_2_ODD TPS_SET_1 TPS_SET_2 TPS_SET_3 TPS_CTL CTL_FFTOSNUM PIR_CTL SNR_CARRIER PPM_CPAMP CAS_CTRL_2 SYR_EPLEP SYR_NUMSYMSTTRACK2K SYR_NUMSYMSTTRACK8K SYR_TRACKCLIPLEVEL SYR_DOPPLER SYR_MISC1 SYR_MISC2 SYR_MISC3 27 28 29 2A 2B 2C 2D 2E 2F 30 31 34 35 36 37 46 47 48 49 4A 4B 4C 4F 51 R R R R R R R/W R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved Reserved Reserved TPS Sync Reserved Reserved Reserved Reserved TPSRCVFrame[1:0] TPSRCV Constellation[1:0] TPSRCVHPCode[2:0] TPSRCVMode[1:0] TPSRCVHierarchy[2:0] TPSRCVLPCode[2:0] TPSRCVGuard[1:0] Reserved TPS Reserved Odd[7:0] Reserved Reserved Reserved Reserved TPSSETHierarchy[2:0] TPSSETLPCode[2:0] Reserved Reserved Reserved Reserved TPS Reserved Odd[13:8] TPSSETFrame[1:0] TPSSET Constellation[1:0] TPSSETHPCode[2:0] Use First TPS Now CTL FFTOSNUM[6:0] Reserved SNR Carrier Number[7:0] Mean Reserved SNR Carrier Number[12:8] PPMContPilotCorrAmp TPS Length Indicator[5:0] Reserved Reserved Reserved Reserved Reserved Signalscf CCS State SYR_EPLEP[3:0] NUMSYMSTTRACK2K[5:0] NUMSYMSTTRACK8K[5:0] FTRACKCLIPLEVEL[2:0] DOPPLERHYSTER[2:0] TTRACKCLIPLEVEL[2:0] FALSEALIASLEVEL[2:0] ONE-PATH SLOPE ENABLE ACSDIS2 Freeze TPS Ignore BCH TPS Disable Update ZEROGUARDBACKOFF[2:0] CCIDETECTLEVEL[2:0] Reserved CIRHOLDBACKOFF[1:0] AGC_PW 12BIT ENABLE Reserved Reserved AUTOGUARDBACKOFF[3:0] FORCEDOFFSET[4:0] CIRHOLDLEVEL[1:0] CIR HOLD DISABLE HALFTIME CONTROL[1:0] AGC ENH ENABLE AGC_ENH_CTL AGC_MEAN_CX AGC_BWREDOFFSET AGC_MINGAIN AGC_MODIFIED_TARGET_I SYR_MISC4 SYR_NUMBINSLOOKBACK 52 53 54 55 56 57 58 R/W R/W R/W R/W R R/W R/W Reserved AGCENHUPDATE[3:0] AGCMEANCX[3:0] AGCBWREDOFFSET[3:0] AGCMINGAIN[7:0] AGC MODIFIED TARGET I[7:0] CCS Count Limit[3:0] Reserved MP Moved Count Limit[3:0] Num Bins LookBack[5:0] New Registers for CXD1968AR SYR_CPLXMFENABLE TEST10 TEST11 59 5A 5B R/W R/W R/W Reserved 8K 1/4 8K 1/8 8K 1/16 8K 1/32 2K 1/4 2K 1/8 2K 1/16 2K 1/32 Reserved TEST10[3] TEST10[2] TEST10[1] TEST10[0] TEST11[5:0] - 46 - CXD1968AR Name SYR_MISC5 AGC_MOD_TARGET_Q AGC_GAIN_3 AGC_GAIN_4 QIC_MISC1 QIC_IQPHASEERR TRL_NOMINALRATE_0 CHC_LEAKAGE TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 AUTORCV_1 AUTORCV_2 CSF_MISC AUTORCV_3 AUTORCV_4 TPS_RESERVED_1_EVEN TPS_RESERVED_2_EVEN DCC_OFFSET_I DCC_OFFSET_Q DCC_MISC FEC Registers FEC_PARAMS BB_PARAMS BER_PERIOD FEC_STATUS SET_SYNC_DETECT LT_QLTY_THRESHOLD Addr. R/W 5C 5F 60 61 62 63 65 6B 6C 6D 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F R/W R R R R/W R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R R R R R R/W 7 Skirtrmv 6 5 Numsymsftrack_lut[2:0] 4 3 2 1 FFT 512 0 Echo stretch Post echo Nttrack chc ext enable AGC_modified_target_q[7:0] Agc_gain_q[7:0] Reserved Reserved QIC Enable IQPhaseErr[7:0] trlnominalrate_0[7:0] Reserved Reserved TEST2[7:0] TEST3[7] Reserved TEST4[7:0] TEST5[7:0] TEST6[7:0] TEST7[7:0] TEST8[7:0] Reserved Activate Scanning Prescale_Val[6:0] XMS_Tuner_Wait[1:0] Reserved Reserved Autorcv_Reserved[3:0] TPS_Reserved_Even[7:0] Reserved TPS_Reserved_Even[13:8] DCC_Offset_I[7:0] DCC_Offset_Q[7:0] Reserved DCC_Gain[1:0] DCC_ Enable TS_Lock_Timeout[4:0] Demod_Status[3:0] Demod_Timeout_2K[3:0] CSF_ Enable TEST3[4:0] CHC_LEAKAGE[3:0] TEST1[0] Agc_gain_q[11:8] QIC Gain[2:0] 80 81 83 84 86 87 88 R/W R/W R/W R R/W R/W R R R R R R/W R/W R/W Tsclk cont Auto clear Ser data on TS parallel Output Sel Measurement msb sel Msb Sel Latch on posedge Tsclk _204 TSsync byte Tri State Outputs Tserr full Rs Disable Tsclk full Tsvalid Tssync Tserr Active Active High Active High High Reserved Ber_ses Ber_es Berest test mode Lck Flag Ber Est Period[4:0] Ts Llck Flag Ts Synch Lock Vtb Sync New Ber es Reserved Synch Cntr Ts Synch Mode Cntr Mode Sync Loss Lddr Length[2:0] LT QLTY THRESHOLD[7:0] BERCNT[7:0] BERCNT[15:8] Synch Lddr Lngth[2:0] BER_ESTIMATE 89 8A 8B 8C 90 91 92 New Estimate Reserved BERCNT overflow CWRJCT CNT[7:0] CWRJCT CNT[15:8] BERCNT[19:16] CWRJCT_CNT VIT_CTRL VIT_SN VIT_ST Rate Sel Reserved Rate[2:0] Reserved SN[9:5] Bert[2:0] Reserved ST[12:9] - 47 - CXD1968AR Name VIT_BER Miscellaneous Registers CHIP_INFO RST_REG INTERRUPT_SOURCE INTERRUPT_MASK TIMEOUT_VAL PLL_FODR PLL_F PLL_CONTROL TUNER_CTRL_5 AUTO_RESET Addr. R/W 93 94 R R 7 6 5 4 VBER[7:0] 3 2 1 0 VBER[15:8] A0 A2 A3 A4 A6 A7 A8 A9 AF B1 B2 B3 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RF/IF AGCQ PWM[1:0] R/W R/W CHANNEL WIDTH[1:0] Reserved Enable quiet i2c PLL power down i2c FET enable Reserved Adc rst Ts if int Ts if int en Cofdm rst Cofdm Int Cofdm Int En CHIP Identification Vit rst Fec rst Reserved Hard Ber_Es Cold Version Warm Rs Cwrjct Flag Rs Cwrjct Flag En Ts synch Ts Llck Flag Reserved Lock Ts Synch Ts Llck Flag En Reserved Ber_Ses Ber_Es En Ber_Ses En TIMEOUT VAL[7:0] OD[1:0] F[7:0] PLL op enable PLL bypass Ext clk enable PLL op invert PLL test mode Clock disable R[4:0] Reserved Reserved Reserved IF AGC EN RF/IF AGCQ MODE disable RF/IF RF/IF AGCQ GPO AGCQ GPI RF_IFAGC_CTRL RF/IF AGCQ PWM[9:2] Reserved RESET DATA PERIOD AUTO UNDER FLOW DELAY[7:0] DATA_PERIOD[7:0] DATA_PERIOD[15:8] Reserved Reserved RST_Q Ext A/D Select Reserved ADC Offset 2s Comp Reserved RINTSEL_Q[2:0] UDF_Q OVF_I UDF_I RINTEN_ I Reserved ADC test mode Reserved DCCEN RST_I CLKRCVEN Reserved Reserved RAM_ STAND BY RINTSEL_I[2:0] Reserved ENABLE OVER FLOW SMOOTH_CTRL B4 SMOOTH_STAT SMOOTH_DELAY SMOOTH_DP ADC_CONTROL ADC_CONTROL2 RAM_CONTROL ADC_CONTROL3 ADC_STATUS B5 B6 B7 B8 B9 BA BC BD BE R/W R/W R/W R/W R/W R/W R/W R/W RINTEN_Q R OVF_Q Reserved REFSEL - 48 - CXD1968AR CXD1968AR COFDM Demodulator Core Registers COR_CTL Offset Address: 0x00 Bit 7:6 5 4 Name Reserved Core Active Hold Set to enable core operation. When "0" the core reverts to and is held in its IDLE mode. This bit will be the normal method of core enable and disable. Set to prevent the state machine from changing state. For debugging only. Core state override control, when a non-zero value is written into these bits the core state machine is forced into a specific state as listed. This field is for debugging only and not expected to be used in normal operation. In particular backward transitions may give rise to unpredictable behavior. Description Default 00 0 0 R/W R/W R/W R/W Read/Write RESET: 0x00 3:0 Core State 0000: State machine not forced 0001: WAIT_TRL 0010: WAIT_AGC 0011: WAIT_SYR 0100: WAIT_PPM 0101: WAIT_TPS 0110: MONITOR _TPS 0111 to 1111: Reserved 0000 R/W COR_STAT Offset Address: 0x01 Bit 7 Name CHC Tracking Read Only Description Set when CHC enters tracking state. Set when "acceptable" TPS data has been received. This depends on a good TPS BCH check (TPS_BCHOK) unless TPS_CTL (TPS Ignore BCH) is set - this differentiates TPS locked from TPS_RCVD_1 (TPSBCHOK). Cleared when the state machine is forced back into the IDLE state. Set when SYR is locked (guard interval and symbol position determined). Set when the AGC is locked. 0000: IDLE 0001: WAIT_TRL 0010: WAIT_AGC 0011: WAIT_SYR 0100: WAIT_PPM 0101: WAIT_TPS 0110: MONITOR _TPS 0111 to 1111: Reserved Default -- R/W R 6 TPS Locked -- R 5 4 SYR Locked AGC Locked -- -- R R 3:0 Core State Current core state -- R - 49 - CXD1968AR COR_INTEN Offset Address: 0x02 Bit 7 6 5 4 3 2 Reserved INTEN SYR SymEnd INTEN FFT Done INTEN AGC Lock Change INTEN TPS RCVD BCHBad Name INTEN Global Read/Write Description Set to enable interrupts COR_INTEN[5:0]. Set to enable an interrupt on SYR symbol end. Set to enable an interrupt on completion of FFT processing. Set to enable an interrupt on change of AGC lock. Set to enable an interrupt on receipt of a TPS block with bad BCH check. This interrupt is NOT influenced by the TPS_CTL (TPS Use BCH) register setting. Set to enable an interrupt on a change of TPS data (except frame number). This interrupt indicates that the contents of the TPS_RCVD_2, 3, 4 registers have changed, this only occurs at the end of a frame. Set to enable an interrupt on receipt of a TPS block. This interrupt indicates that the TPS_RCVD_1, 2, 3, 4 registers have been updated, this only occurs at the end of a frame. RESET: 0x00 Default 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 1 INTEN TPS RCVD Changed 0 R/W 0 INTEN TPS RCVD Update 0 R/W COR_INTSTAT Offset Address: 0x03 Bit 7:6 5 4 3 2 Reserved INTSTAT SYR SymEnd INTSTAT FFT Done INTSTAT AGC Lock Change INTSTAT TPS BCHBad Name Read/Write Description Interrupt on SYR symbol end. Interrupt on FFT complete. Interrupt on change of AGC lock. Interrupt on receipt of a TPS block with bad BCH check. Interrupt on a change of TPS data (except frame number). Interrupt on receipt of a TPS block. RESET: 0x00 Default 00 0 0 0 Write a "1" to the appropriate bit to clear the interrupt flag. 0 R/W R/W R/W R/W R/W R/W 1 0 INTSTAT TPS RCVD Changed INTSTAT TPS RCVD Update 0 0 R/W R/W - 50 - CXD1968AR COR_MODEGUARD Offset Address: 0x04 Bit 7 6:4 Name ZIF_ENABLE Reserved Read/Write Description If set, Zero IF interface is enabled. The core expects the presence of both I and Q channels. If set, this forces the core to use the set mode and guard. The core will not attempt to lock to any other mode and guard even if they are set incorrectly. 0: Mode = 2K 1: Mode = 8K Sets the mode for which the core attempts lock. Only applicable if Force = 1. If the mode is known then setting the mode here will reduce lock times. Sets the guard interval for which the core attempts initial lock. If this is set incorrectly then the core will still automatically recover the correct guard. If the guard is known then setting the guard here will reduce lock times. RESET: 0x00 Default 0 000 R/W R/W R/W 3 Force 0 R/W 2 Mode 0 R/W 1:0 Guard 00: Guard interval = 1/32 01: Guard interval = 1/16 10: Guard interval = 1/8 11: Guard interval = 1/4 00 R/W AGC_CTL Offset Address: 0x05 Bit Name Read/Write Description Once the AGC has locked, the core begins acquisition. Setting these bits allows this to be delayed. The length of time delayed is DelayStartup x 4 symbols (in 8K mode) or DelayStartup x 16 symbols (in 2K mode). For example a value of DelayStartup = 3 will delay the acquisition by ~11ms in with a 1/32 guard (i.e. 12 8K-symbols or 48 2K-symbols). After the COR_CTL (Core Active) bit has been set, then a value of zero in this bit will cause the AGC to start at mid range and the DAGC to start at a gain of "1". In this instance it is necessary to wait for the external RC to settle. If this bit is set then the AGC and DAGC will retain their last gain settings which is useful for reducing lock times for reacquisition after loss of lock. 00: No reduction 01: Reduce BW by 2 10: Reduce BW by 4 (Default) 11: Reduce BW by 8 When the AGC loop locks the BW of the loop is reduced by the following factors. RESET: 0x08 Default R/W 7:5 Delay Startup 000 R/W 4 AGC Use Last Value 0 R/W 3:2 AGCBW Reduction 10 R/W 1 AGC Neg When set, the AGC level output decreases when a larger signal is required, otherwise the AGC level output increases when a larger signal is required. When set, the AGC output gain control value is set to AGC Manual. The AGC continues to monitor the received signal level. 0 R/W 0 AGC Set 0 R/W - 51 - CXD1968AR AGC_MANUAL_1 Offset Address: 0x06 Bit 7:0 Name AGC Manual Read/Write Description AGC manual setting bits 7:0 RESET: 0x00 Default 00h R/W R/W AGC_MANUAL_2 Offset Address: 0x07 Bit 7:4 3:0 Name Reserved AGC Manual Read/Write Description AGC manual setting bits 11:8 RESET: 0x00 Default 0000 0000 R/W R/W R/W Note) 1. In the time interval between host writes to AGC_MANUAL_1 and AGC_MANUAL_2, the manual control to the AGC will have an intermediate value. 2. AGC Manual has been extended by 2 bits for the CXD1968AR and CXD1976R compared to the CXD1973Q. AGC_MANUAL_2[3:2] were previously reserved bits that are now used for this purpose. 3. AGC_MANUAL is a 2's compliment value. AGC_TARGET Offset Address: 0x08 Bit 7:0 Name AGC Target Read/Write Description AGC target bits 7:0. This register sets the base AGC target level. RESET: 0x28 Default 28h R/W R/W Note) The default value will give 12.5dB headroom with 1Vp-p ADC input range for gaussian signals. AGC_GAIN_1 Offset Address: 0x09 Bit 7:0 Name AGC Gain I Read Only Description Current (or latched) AGC gain bits 7:0 Read/Write Description If set, the input signal to AGC is a DC-free signal, provided DCC is enabled. AGC locked indication on the Q channel AGC locked indication on the I channel AGC locked indication Current (or latched) AGC gain bits 11:8 Default -- R/W R/W AGC_GAIN_2 Offset Address: 0x0A Bit 7 6 5 4 3:0 Name AGC_AFTER_DCC LOCK_Q LOCK_I AGC Locked AGC Gain I RESET: 0x00 Default 0 0 0 0 0 R/W R/W R R R R Note) 1. AGC gain is the AGC value in normal operation, but is NOT influenced by AGC_CTL (AGC Set). Refer to PIR_CTL register description for details of the latched mode. 2. The AGC gain range read back is -2048 to +2047. 3. AGC Gain has been extended by 2 bits for the CXD1968AR and CXD1976R compared to the CXD1973Q. AGC_GAIN_2[3:2] were previously reserved bits that are now used for this purpose. - 52 - CXD1968AR ITB_CTL Offset Address: 0x0B Bit 7:1 0 Name Reserved Spec Invert Read/Write Description Set to allow reversed frequency spectrum from tuner RESET: 0x00 Default 00h 0 R/W R/W R/W ITB_FREQ_1 Offset Address: 0x0C Bit 7:0 Name ITB Frequency[7:0] Read/Write Description Bits 7:0 of ITB frequency Read/Write Name Description Bits 13:8 of ITB frequency RESET: 0x00 See table below for recommended values. Default 00h R/W R/W ITB_FREQ_2 Offset Address: 0x0D Bit 7:6 5:0 Reserved ITB Frequency[13:8] RESET: 0x30 See table below for recommended values. Default 00 30h R/W R/W R/W Note) The ITB_FREQ_1, 2 registers set the nominal IF frequency that is expected to be sampled by the ADC. - 1 x F IF ITBFREQ = -------------------- x 16384 F ADC If the IF is being undersampled (e.g. for High IFs) then FIF is the subsampled IF equal to; 2 x FADC - FIF. e.g. for 36.125MHz IF with a 20.48MHz ADC clock, FIF = 4.835MHz. IF [MHz] 4.57 36.00 36.125 36.1667 36.1667 36.0 FIF [MHz] 4.57 4.96 4.835 4.7933 4.8333 5.0 FADC [MHz] 20.48 20.48 20.48 20.48 20.50 20.50 ITBFREQ -3657 (31B7h) -3968 (3080h) -3868 (30E4h) -3835 (3105h) -3863 (30E9h) -3996 (3064h) - 53 - CXD1968AR CAS_CTL Offset Address: 0x0E Bit Name Read/Write Description Enable co-channel interference suppression (CCS) continuously within the CAS block. The CCS is off by default during normal operation, but is enabled automatically if CCI is detected regardless of the setting of this bit. Disable first stage of adjacent channel interference suppression within the CAS block. The first stage of ACS is on by default. The second stage can be enabled by CAS_CTRL_2 register for increased ACI rejection in 1 SAW tuner designs. Disable the digital AGC within the CAS block. The digital AGC is on by default 00: No reduction 01: Reduce BW by 2 10: Reduce BW by 4 (default) 11: Reduce BW by 8 Reduce DAGC BW once the SYR has locked. RESET: 0x14 Default R/W 7 CCS Enable 0 R/W 6 ACS Disable 0 R/W 5 DAGC Disable 0 R/W 4:3 DAGCBW Reduction 10 R/W 2:0 CCSMU Set the BW of the co-channel suppression filter. A large value corresponds to wide BW and vice versa. The reset value of 4 gives good performance for PAL interference. 100 R/W Note) This diagram illustrates the selection logic for control of the CCI filter. I2C CAS_CTL Bit-7 (CCS_Enable) CCS_Enable I2C CAS_CTRL_2 Bit-1 (CCS_State) Enhanced Symbol Tracking Block CCI Detected Incoming Samples CCI Rejection Circuit Filtered Samples - 54 - CXD1968AR CAS_FREQ Offset Address: 0x0F Bit Name Read/Write Description Sets the center frequency of the co-channel suppression filter. The actual frequency (in MHz) is equal to; CCS center frequency = CCS_Freq x channel BW / 224 RESET: 0xB3 Default R/W 7:0 CCS_Freq CCS_Freq is an 8-bit signed number and the reset value of -77 corresponds to a center of frequency of -2.75MHz in 8MHz channels. This is the same frequency as the vision carrier of PAL signals and thus centers the co-channel suppression filter on the vision carrier. B3h R/W Note) 1. The co-channel suppression filter is automatically enabled by the enhanced symbol tracking block to remove co-channel interference whenever it is detected. It is also automatically enabled during acquisition. It is therefore important to program the CAS_FREQ register with the nominal frequency of the vision carrier of the likely CCI interference. Example values are given below. 2. For optimum performance this setting should be modified if the transmitter carrier frequency is offset, also shown in this table. Vision carrier nominal position [MHz] -1.75 -2.25 -2.75 Channel BW [MHz] 6 7 8 CCS_Freq for COFDM offset CCS_Freq = (Fvc - Foffset) x 224 / BW -500kHz -47 (D1h) -56 (C8h) -63 (C1h) -333kHz -53 (CBh) -61 (C3h) -68 (BCh) -166kHz -59 (C5h) -67 (BDh) -72 (B8h) 0kHz -65 (BFh) -72 (B8h) -77 (B3h) 166kHz -72 (B8h) -77 (B3h) -82 (AEh) 333kHz -78 (B2h) -83 (ADh) -86 (AAh) 500kHz -84 (ACh) -88 (A8h) -91 (A5h) CAS_DAGCGAIN Offset Address: 0x10 Bit Name Read Only Description Digital automatic gain controller gain indication from CAS block. The actual gain of the digital AGC can be read from this register and is coded as follows. Actual gain = CAS DAGC Gain / 16 Therefore a gain of "1" is equivalent to a setting of "16" in this register. Default R/W 7:0 CAS DAGC Gain -- R TEST9 Offset Address: 0x11 Bit 7 6:3 2 1 0 Name TEST9[7] TEST9[6:3] TEST9[2] TEST9[1] TEST9[0] Read/Write Description RESET: 0x00 Default 0 00h 0 0 0 R/W R/W R/W R/W R/W - 55 - CXD1968AR SYR_STAT Offset Address: 0x12 Bit 7:6 5 4 3 2 Name Reserved TEST5 SYR Locked Reserved SYR Mode 0: 2K 1: 8K 00: 1/32 01: 1/16 10: 1/8 11: 1/4 Read Only Description Default -- -- SYR locked indication (guard detection and symbol position determined) -- -- SYR detected mode -- R/W R R R R R 1:0 SYR Guard SYR detected guard interval -- R FFT_CTL Offset Address: 0x17 Bit 7:3 2 1 0 Name Reserved FFT Test Trigger FFT Manual Mode FFT Inverse Transform Read/Write Description A "0" to "1" transition causes the FFT to be triggered to perform an FFT on its current input buffer. Software should write "1" then "0" to this bit. Set to disable FFT input buffer filling with off-air data. Inverse FFT selection. Set to "0" for normal OFDM demodulation. RESET: 0x00 Default 00h 0 0 0 R/W R/W R/W R/W R/W SCR_CTL Offset Address: 0x18 Bit 7 Name Reserved 000: 1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 110: 1/64 111: 1/128 Read/Write Description RESET: 0x30 Default 0 R/W R/W 6:4 SYR Adjust Decay These bits are not used in the CXD1968AR. 011 R/W 3:2 1 0 Reserved SCR No Common Phase SCR Disable Set to disable common phase error correction. Set to disable carrier phase slope correction. Note that this is not compatible with SYR tracking, so SYR_CTL (SYR Tracking Disable) must also be set. 00 0 0 R/W R/W R/W - 56 - CXD1968AR PPM_CTL_1 Offset Address: 0x19 Bit 7 6:4 3 Name Reserved PPMMaxFreq Reserved Read/Write Description Maximum search range setting for coarse frequency offset. If set, equalizes the frequency range in Hz searched in 2K and 8K modes. If clear, the search range in Hz is 4 times larger in 2K mode than in 8K mode, which can unnecessarily increase acquisition time in 2K mode. This setting is backward compatible with the CXD1973Q. Set to disable scattered pilot correlation. If disabled, acquisition is slowed down because the demodulator must wait for all TPS configuration before it can complete the acquisition sequence. The recommended setting for this bit is "0". Set to bypass continuous pilot correlator. RESET: 0x10 See table below for settings. Default 0 001 0 R/W R/W R/W R/W 2 Reduced Search Time Enable 0 R/W 1 0 PPM Disable FindScat Pilots PPM Bypass Corr 0 0 R/W R/W Note) The CXD1968AR can acquire a wider range of frequency offsets than the CXD1973Q. The table below shows the ranges that may be programed using PPMMaxFreq. Reduce search time enable 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PPM Max Freq 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 2K search range FFT bins 31 63 127 255 383 511 639 767 31 31 31 63 63 127 127 255 Channel [kHz] 8MHz 138.4 281.3 567.0 1138.4 1709.8 2281.3 2852.7 3424.1 138.4 138.4 138.4 281.3 281.3 567.0 567.0 1138.4 7MHz 121.1 246.1 496.1 996.1 1496.1 1996.1 2496.1 2996.1 121.1 121.1 121.1 246.1 246.1 496.1 496.1 996.1 6MHz 103.8 210.9 425.2 853.8 1282.4 1710.9 2139.5 2568.1 103.8 103.8 103.8 210.9 210.9 425.2 425.2 853.8 FFT bins 31 63 127 255 383 511 639 767 31 63 127 255 383 511 639 767 8K search range Channel [kHz] 8MHz 34.6 70.3 141.7 284.6 427.5 570.3 713.2 856.0 34.6 70.3 141.7 284.6 427.5 570.3 713.2 856.0 7MHz 30.3 61.5 124.0 249.0 374.0 499.0 624.0 749.0 30.3 61.5 124.0 249.0 374.0 499.0 624.0 749.0 6MHz 25.9 52.7 106.3 213.4 320.6 427.7 534.9 642.0 25.9 52.7 106.3 213.4 320.6 427.7 534.9 642.0 166kHz transmit offset networks 333kHz transmit offset networks 500kHz transmit offset networks Compatible with the CXD1973Q Compatible with the CXD1973Q Compatible with the CXD1973Q Compatible with the CXD1973Q Remarks - 57 - CXD1968AR TRL_CTL Offset Address: 0x1A Bit 7 6:3 2:0 Name Reserved TRL Track Gain Factor TRL Loop Gain Read/Write Description Additional gain (x/16) applied during tracking (default is to reduce gain by 1/8 during tracking). Sets the gain (x/16) of the sample timing loop during acquisition. Also sets the gain (combined with TRL track gain factor) during tracking. RESET: 0x14 Default 0 0010 100 R/W R/W R/W R/W TRL_NOMINALRATE_1 Offset Address: 0x1B Bit 7:0 Name TRL Nominal Rate Read/Write Description Bits 15:8 of TRL nominal rate Read/Write Description Bits 23:16 of TRL nominal rate RESET: 0x00 See table below for recommended values. Default 00h R/W R/W TRL_NOMINALRATE_2 Offset Address: 0x1C Bit 7:0 Name TRL Nominal Rate RESET: 0x80 See table below for recommended values. Default 80h R/W R/W Note) 1. The TRL_NOMINALRATE is a 24-bit non-contiguous register comprising three 8-bit registers called TRL_NOMINALRATE_2, TRL_NOMINALRATE_1 and TRL_NOMINALRATE_0. Also see the TRL_NOMINALRATE_0 register at address 0x65. 2. Sets the nominal rate of the sample timing NCO. This can be used to allow reduced bandwidth (6 and 7MHz) operation without changing crystal or tuner clock reference frequencies. TRL nominal rate is the ratio of the FFT time sample clock to the (fixed) ADC clock frequency. 16 x ChanBW 24 TRLNOMINALRATE = ------------------------------------- x ( 2 ) F ADC x 7 The maximum allowable value of this register is 16777215. The minimum TRL nominal rate is 11184810.66 = AAAAABh. Some common settings are given below for a 20.48MHz crystal supplying the ADC clock, or from a 20.5MHz ADC clock derived from the PLL output. Channel bandwidth 8MHz 7MHz 6MHz FADC = 20.48MHz 14979657 (E49249h) 13107200 (C80000h) 11234743 (AB6DB7h) FADC = 20.5MHz 14965043 (E45933h) 13094412 (C7CE0Ch) 11223782 (AB42E6h) - 58 - CXD1968AR TRL_TIME_1 Offset Address: 0x1D Bit 7:0 Name TRL Timing Offset Read Only Description Current (or latched) bits 7:0 of TRL timing offset Read Only Description Current (or latched) bits 15:8 of TRL timing offset Default -- R/W R Default -- R/W R TRL_TIME_2 Offset Address: 0x1E Bit 7:0 Name TRL Timing Offset Note) 1. Refer to PIR_CTL register description for details of the latched mode. The timing offset in ppm is equal to; Offset (ppm) = 1e6 x TRL timing offset / TRL_NOMINALRATE / 16 Example: for 8MHz OFDM using a 20.48MHz crystal Offset (ppm) = TRL timing offset / 239.67 2. TRL timing offset is a signed quantity, in two's complement format. CRL_CTL Offset Address: 0x1F Bit 7 6:3 2:0 Name CRL Disable Fine CRL Track Gain Factor CRL Loop Gain Read/Write Description Set to disable SYR fine offset correction on CRL during acquisition. Additional gain (x/16) applied during tracking (default is to reduce gain by 1/4 during tracking). Sets the gain (x/16) of the carrier loop during acquisition. Also sets the gain (combined with CRL track gain factor) during tracking. RESET: 0x24 Default 0 0100 100 R/W R/W R/W R/W - 59 - CXD1968AR CRL_FREQ_1 Offset Address: 0x20 Bit 7:0 Name CRL Frequency Offset Read Only Description Current (or latched) bits 7:0 of CRL frequency offset Read Only Name Description Current (or latched) bits 15:8 of CRL frequency offset Read Only Name Description Sign extension: CRL frequency offset (23) CRL frequency offset (22) Current (or latched) bits 22:16 of CRL frequency offset Default -- -- R/W R R Default -- R/W R Default -- R/W R CRL_FREQ_2 Offset Address: 0x21 Bit 7:0 CRL Frequency Offset CRL_FREQ_3 Offset Address: 0x22 Bit 7 6:0 SEXT CRL Frequency Offset Note) 1. Refer to PIR_CTL register description for details of the latched mode. 2. The following relationships are defined: The carrier offset in FFT bins is equal to CRL frequency offset / 4096. For 2K mode, the carrier offset frequency (Hz) is equal to; CRL frequency offset x 1.0899 in 8MHz channel CRL frequency offset x 0.9537 in 7MHz channel CRL frequency offset x 0.8174 in 6MHz channel For 8K mode, the carrier offset frequency (Hz) is equal to; CRL frequency offset x 0.2725 in 8MHz channel CRL frequency offset x 0.2384 in 7MHz channel CRL frequency offset x 0.2044 in 6MHz channel 3. The value read back from the combined CRL_FREQ_1, CRL_FREQ_2, CRL_FREQ_3 registers in the CXD1968AR and CXD1976R is 1/4 of the value read back by the same registers in the CXD1973Q due to the increased frequency offset search range of the CXD1968AR and CXD1976R. 4. CRL frequency offset is a signed quantity, in two's complement format. - 60 - CXD1968AR CHC_CTL_1 Offset Address: 0x23 Bit Name 000: gain = 0 001: gain = 1/32 010: gain = 1/16 011: gain = 1/8 100: gain = 1/4 101: gain = 1/2 110, 111: gain = 1 Read/Write Description RESET: 0x01 Default R/W 7:5 Mean Pilot Gain Sets the mean pilot gain used in the channel predictor if the manual mean pilot bit is set. 000 R/W 4 3 2 1 0 Manual Mean Pilot Disable Bad Pilots Disable Noise Normal Disable CHC Predictor CHC Interpolator Set to allow the mean pilot gain to take on the value in bits 5:7. In normal operation the mean pilot gain is adaptively adjusted to suit the channel conditions. Set to disable bad pilots from being dropped in the PPM. Set to disable noise normalization between scattered and continuous pilots. Set to disable the adaptive time domain prediction on the pilots. 0: Linear 1: FIR Sets the frequency domain interpolation method used. 0 0 0 0 1 R/W R/W R/W R/W R/W CHC_SNR Offset Address: 0x24 Bit Name Read Only Description Estimated signal-to-noise ratio (SNR) in dB. The value in this register either gives the average SNR of the channel or the SNR of a selected pilot as defined in the CHC_SNR_CARRIER register. The estimated value is independent of the channel response, and accurate to about 1dB. CHC_SNR SNR [ dB ] = -----------------------------8 Note: The value compresses near the extremes. Default R/W 7:0 CHC SNR -- R - 61 - CXD1968AR BDI_CTL Offset Address: 0x25 Bit 7:2 1 0 Name Reserved BDI LPSelect Reserved Read/Write Description 0: HP data and code rate 1: LP data and code rate Selects priority of data for output to the FEC. NB: Do not set this bit to "1". RESET: 0x00 Default 00h 0 0 R/W R/W R/W R/W DMP_CTL Offset Address: 0x26 Bit 7:1 0 Reserved DMP Disable CSI Weight Name Read/Write Description Set to disable soft decision weighting by CSI. RESET: 0x00 Default 00h 0 R/W R/W R/W TPS_RCVD_1 Offset Address: 0x27 Bit 7 6 5 Reserved TPS RCVD Changed Flag TPS RCVD BCHOK Flag Name Read Only Description Set when an update to TPS_RCVD_2, 3, 4 caused the data contents of the registers to change. Set if the BCH check on the TPS data of the previous frame was correct. This bit is NOT influenced by TPS_CTL (TPS Use BCH). Set if a TPS sync sequence was received. If the control state machine is in MONITOR_TPS, then this bit indicates presence/absence of a sync sequence in the previous frame (updated every time a new TPS frame is received). If the control state machine is NOT in MONITOR_TPS then this bit asserts as soon as a sync sequence is detected, deasserting if the BCH check subsequently fails. Frame number (within super-frame) indicated by TPS data received in the previous frame. Default -- -- -- R/W R R R 4 TPS RCVD Sync Flag -- R 3:2 1:0 Reserved TPSRCVFrame -- -- R R - 62 - CXD1968AR TPS_RCVD_2 Offset Address: 0x28 Bit 7 Name Reserved Read Only Description 000: Non hierarchical 001: = 1 010: = 2 011: = 4 100 to 111: Reserved 00: QPSK 01: QAM-16 10: QAM-64 11: Reserved Default -- Hierarchy information for current scheme R/W R 6:4 TPSRCVHierarchy -- R 3:2 1:0 Reserved TPSRCVConstellation Constellation for current modulation scheme -- -- R R TPS_RCVD_3 Offset Address: 0x29 Bit 7 Name Reserved Read Only Description 000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101 to 111: Reserved 000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101 to 111: Reserved Default -- R/W R 6:4 TPSRCVLPCode Low priority stream code rate -- R 3 Reserved -- R 2:0 TPSRCVHPCode High priority stream code rate -- R TPS_RCVD_4 Offset Address: 0x2A Bit 7:6 5:4 3:2 1:0 Name Reserved TPSRCVGuard Reserved TPSRCVMode 00: 2K Mode 01: 8K Mode 10, 11: Reserved 00: 1/32 01: 1/16 10: 1/8 11: 1/4 Read Only Description Default -- Guard interval -- -- Transmission mode information -- R/W R R R R - 63 - CXD1968AR TPS_RESERVED_1_ODD Offset Address: 0x2B Bit 7:0 Name CELLID[15:8] Read Only Description TPS reserved bits S40-S47 representing Cell-ID bits 15:8 respectively, received in TPS frame numbers 1 and 3. Default -- R/W R TPS_RESERVED_2_ODD Offset Address: 0x2C Bit 7:6 5 Reserved TimeSliced Data Name Read Only Description TPS reserved bit S48 - DVB-H time sliced data present in received data. In hierarchical mode, these bits correspond to HP stream. TPS reserved bit S49 - DVB-H MPE-FEC encoded data present in received data. In hierarchical mode, these bits correspond to HP stream. TPS reserved bits S50-S53 received during TPS frame numbers 1 and 3. Default R/W -- R 4 3:0 MPE-FECData TPS_RESERVED_ODD -- -- R R TPS_SET_1 Offset Address: 0x2D Bit 7:2 Name Reserved Read/Write Description Current frame number within super-frame as maintained by internal counters. The frame number is required to determine super-frame boundaries (for TPS_SET_x updates). The frame counter is initialized to the first received TPS frame data (TPSRCVFrame), i.e., TPS data received while the control state machine is in the WAIT_TPS state. RESET: 0x00 Default 00h R/W R/W 1:0 TPSSETFrame The symbol counter increments at end of FFT processing. The frame counter increments when the symbol counter wraps from 67 to 0. With the control state machine in IDLE, writes to TPS_SET_1 take immediate effect. Otherwise, setting by the host takes effect at the beginning of the next frame (when FFT output symbol number wraps from 67 to 0). Only then will the register read-back the data written by the host. 00 R/W - 64 - CXD1968AR TPS_SET_2 Offset Address: 0x2E Bit 7 Name Reserved Read/Write Description 000: Non hierarchical 001: = 1 010: = 2 011: = 4 100 to 111: Reserved 00: QPSK 01: QAM-16 10: QAM-64 11: Reserved RESET: 0x00 Default 0 Hierarchy information for current scheme R/W R/W 6:4 TPSSETHierarchy 000 R/W 3:2 1:0 Reserved TPSSETConstellation Constellation for current modulation scheme 00 00 R/W R/W Note) 1. Data in this register corresponds to the actual parameters used by the core. 2. This register is updated (If TPS_CTL -TPS Disable Update is NOT set) from TPS_RCVD_2 when TPSSETFrame transitions from "3" to "0" (super-frame). Notice that the timing of the update does not coincide with updates to the TPS_RCVD_2 register. 3. With the control state machine in IDLE, writes to TPS_SET_2 take immediate effect. Otherwise, setting by the host takes effect at the beginning of the next super-frame. Only then will the register read-back the data written by the host. TPS_SET_3 Offset Address: 0x2F Bit 7 Name Reserved Read/Write Description 000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101 to 111: Reserved 000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101 to 111: Reserved RESET: 0x00 Default 0 R/W 6:4 TPSSETLPCode Low priority stream code rate 000 R/W 3 Reserved 0 R/W 2:0 TPSSETHPCode High priority stream code rate 000 R/W Note) 1. Data in this register corresponds to the actual parameters used by the core. 2. This register is updated (If TPS_CTL -TPS Disable Update is NOT set) from TPS_RCVD_3 when TPSSETFrame transitions from "3" to "0" (super-frame). Notice that the timing of the update does not coincide with updates to the TPS_RCVD_3 register. 3. With the control state machine in IDLE, writes to TPS_SET_3 take immediate effect. Otherwise, setting by the host takes effect at the beginning of the next super-frame. Only then will the register read-back the data written by the host. - 65 - CXD1968AR TPS_CTL Offset Address: 0x30 Bit 7:3 Name Reserved Read/Write Description By default, TPS_SET_2, 3 registers are updated from TPS_RCVD_2, 3 when TPSSetFrame transitions from "3" to "0" (super-frame). If this bit is set, then the FIRST acceptable TPS RCVD data (while state-machine is in WAIT_TPS) is loaded into the TPS_SET_2, 3 registers irrespective of TPS RCVD Frame number. This could assist faster acquisition, except in the superframe immediately prior to a parameter change. By default, TPS RCVD and TPS SET registers are updated only if the BCH check is OK ("good TPS"). When TPS Ignore BCH is set both TPS_RCVD and TPS_SET registers are updated irrespective of the BCH check. When set, this bit disables updating of the "SET" TPS data from "RCVD" TPS data in the data stream. RESET: 0x04 Default 00h R/W R/W 2 Use First TPS Immediately 1 R/W 1 TPS Ignore BCH TPS Disable Update 0 R/W 0 0 R/W CTL_FFTOSNUM Offset Address: 0x31 Bit 7 Name Reserved Read Only Description FFT output symbol number counter (0...63). This counter increments every symbol when new symbol data is available at the output of the FFT. A value of 127 read from this register implies that the counter is not yet running (symbol number is not valid). Default -- R/W R 6:0 CTL FFTOSNUM -- R PIR_CTL Offset Address: 0x34 Bit 7:1 Name Reserved Read/Write Description AGC_GAIN, TRL_TIMEOFF, CRL_FREQOFF and BER_ESTIMATE are fields more than 8 bits which are each accommodated in more than one register. It is therefore possible for the field value to change in the time between the two reads from the register pair. When a "1" is written to the freeze bit (whether it was previously "0" or not), the field values are latched. With the freeze bit "0" the data within the fields changes dynamically. RESET: 0x00 Default 00h R/W R/W 0 Freeze 0 R/W - 66 - CXD1968AR SNR_CARRIER_1 Offset Address: 0x35 Bit Name Read/Write Description Bits 7:0 of SNR_CARRIER. The 13 bits of the SNR carrier number specify which carrier's SNR is output in the CHC_SNR register allowing the SNR of each carrier to be monitored. Note: Once this register has been set then it may take up to 1 symbol (~1ms in 8K, ~0.25ms in 2K) for the CHC_SNR register to contain the correct value. RESET: 0x00 Default R/W 7:0 SNR Carrier Number 00h R/W SNR_CARRIER_2 Offset Address: 0x36 Bit 7 6:5 Mean Reserved Name Read/Write Description If set, this outputs the means SNR of all the continuous pilots in the CHC_SNR register, otherwise the SNR of the specified carrier is output. Bits 12:8 of SNR_CARRIER. The 13 bits of the SNR carrier number specify which carrier's SNR is output in the CHC_SNR register allowing the SNR of each carrier to be monitored. Note: Once this register has been set then it may take up to 1 symbol (~1ms in 8K, ~0.25ms in 2K) for the CHC_SNR register to contain the correct value. RESET: 0x80 Default 1 00 R/W R/W R/W 4:0 SNR Carrier Number 00h R/W PPM_CPAMP Offset Address: 0x37 Bit Name Read Only Description This value is the output of the PPM continuous pilot correlator. During continuous pilot correlation, it holds the peak detected value, at the end of scattered pilot correlation shows the peak detected value, and during normal operation shows a running measurement of the continuous pilot correlation. A value below 20 (2K) or 80 (8K) indicates that the OFDM signal may have disappeared, or is extremely noisy. A peak value of 42 or 176 (2K or 8K respectively) is attained with a perfect signal. Default R/W 7:0 PPMContPilotCorrAmp -- R - 67 - CXD1968AR CAS_CTRL_2 Offset Address: 0x46 Bit Name Read/Write Description TPS bits S17-S22 - Indicates length of valid TPS data. Common values are; 0x17 (DVB-T no cell ID) 0x1F (DVB-T/H with cell ID) 0x21 (DVB-H with cell ID and TimeSlice and MPE-FEC signaled via TPS bits) Indicates status of CCS filter. 0: CAS CCS filter not active 1: CAS CCS filter active Disable CAS block 2nd ACI filter stage. RESET: 0x01 Default R/W 7:2 TPS_LENGTH_INDICATOR 00h R/W 1 0 CCS_STATE ACSDIS2 0 1 R R/W SYR_EPLEP Offset Address: 0x47 Bit 7 6:4 3:0 Name Reserved signalscf syr_eplep[3:0] Read/Write Description Noise rms level scale factor - determines lowest level of echo that can be equalized. Edge of guard allowance in samples to optimize post-cursive long echo performance. RESET: 0x2F Default 0 010 1111 R/W R/W R/W R/W SYR_NUMSYMSTTRACK2K Offset Address: 0x48 Bit 7:6 5:0 Name Reserved NUMSYMSTTRACK2K Read/Write Description This register controls, for 2K mode, the duration of each symbol tracking period, in number of symbols, for the enhanced tracking block in time domain tracking mode. RESET: 0x10 Default 00 10h R/W R/W R/W SYR_NUMSYMSTTRACK8K Offset Address: 0x49 Bit 7:6 5:0 Name Reserved NUMSYMSTTRACK8K Read/Write Description This register controls, for 8K mode, the duration of each symbol tracking period, in number of symbols, for the enhanced tracking block in time domain tracking mode. RESET: 0x10 Default 00 10h R/W R/W R/W - 68 - CXD1968AR SYR_TRACKCLIPLEVEL Offset Address: 0x4A Bit 7:6 Name Reserved Read/Write Description Sets the threshold of useful equalization i.e. the level of any echo path that must be equalized relative to the frequency domain noise floor. The default value of 4 relates to an echo level at approximately -21dB of the main path. (0: Lowest level, 7: Highest level). Sets the threshold of useful equalization i.e. the level of any echo path that must be equalized relative to the time domain noise floor. The default value of 2 relates to an echo level at approximately -21dB of the main path. (0: Lowest level, 7: Highest level). RESET: 0x22 Default 00 R/W R/W 5:3 FTRACKCLIPLEVEL 100 R/W 2:0 TTRACKCLIPLEVEL 010 R/W SYR_DOPPLER Offset Address: 0x4B Bit 7:6 Name Reserved Read/Write Description Sets the number of tracking periods during which the enhanced symbol tracker must observe a persistent change in the channel profile before reacting to it. Increasing this register value prevents the symbol tracker reacting to spurious and/or transient events. Sets the threshold level (FALSEALIASLEVEL) for valid path energy detection in the channel transfer function used for symbol tracking. RESET: 0x14 Default 00 R/W R/W 5:3 DOPPLERHYSTER 010 R/W 2:0 FALSEALIASLEVEL 100 R/W SYR_MISC1 Offset Address: 0x4C Bit Name Read/Write Description Sets threshold that must be satisfied to provide enough certainty to an auto-guard/mode detection outcome of 2K, 1/32. Lower to tighten the decision and increase to loosen the decision. Sets the threshold that must be satisfied to provide enough certainty on the auto-guard/mode detection outcome. Lower to tighten the decision and increase to loosen the decision. Allows single path channels to be treated as long post-cursive or pre-cursive channels. RESET: 0xFE Default R/W 7:5 ZEROGUARDBACKOFF 111 R/W 4:1 AUTOGUARDBACKOFF 1111 R/W 0 ONEPATH SLOPE ENABLE 0 R/W - 69 - CXD1968AR SYR_MISC2 Offset Address: 0x4F Bit 7:5 Name CCIDETECTLEVEL Read/Write Description Sets the threshold for turning on the CAS block co-channel suppression filter if CCI has been detected. Causes the enhanced symbol tracker to consistently shift the FFT window for each symbol by FORCEDOFFSET samples i.e. cause the FFT window to be early by FORCEDOFFSET samples. Use with modest values in doppler channels. RESET: 0x85 Default 100 R/W R/W 4:0 FORCEDOFFSET 00101 R/W Note) 1. The CCS filter is turned on whenever CCI is detected, and during acquisition even if the CCS Enable bit (bit 7 of the CAS_CTL register) is clear, so it is important that the CAS_FREQ register is set to the correct frequency to cancel the vision carrier of any CCI present. See description of the CAS_FREQ register. 2. Ensure that CCS is disabled prior to acquisition. Failure to do so will prevent automatic selection of CCS. SYR_MISC3 Offset Address: 0x51 Bit 7 Name Reserved Read/Write Description Sets the amount of reduction to apply to the CIR averaging where the averaging of the CIR from symbol to symbol is; avCIR = avCIR + curCIR x 2 - Sets the power threshold which the CIR has to exceed to be deemed stable during an enhanced tracking period so that reduced CIR averaging can take place. 0: Reduces averaging of the CIR in the enhanced tracker when the CIR profile is seen to be stable during a tracking period - desirable for time varying channels. 1: Maintain full averaging through out the tracking period. Sets the calculation method for the duration of a tracking period (in symbols) for the enhanced tracker. 00: Duration fixed to NUMSYMSTTRACK2K or NUMSYMSTTRACK8K. RESET: 0x6A Default 0 R/W R/W 6:5 CIRHOLDBACKOFF 11 R/W 4:3 CIRHOLDLEVEL 01 R/W 2 CIRHOLD DISABLE 0 R/W 1:0 HALFTIMECONTROL 01: Duration alternates between N and 0.5N where N is either NUMSYMSTTRACK2K for 2K mode and NUMSYMSTTRACK8K for 8K mode. 10: Duration determined randomly from period to period. Ideal for time varying channels. 11: Reserved 10 R/W - 70 - CXD1968AR AGC_ENH_CTL Offset Address: 0x52 Bit 7:6 5 Reserved AGC_PWM12BITENABLE Name Read/Write Description When set the 12-bit AGC and PWM is selected. This gives 12-bit resolution on the IFAGC PWM output instead of 10-bit resolution on the CXD1973Q. Enhanced AGC update rate. These bits determine the rate (in ADC samples) at which the AGC target level is updated when the enhanced AGC is enabled. The update rate in samples is given by; Samples per update = (AGCENHUPDATE + 1) x 8192 The default is 57,344 samples. Enhanced AGC enable. When set, the AGC target level set by the AGC_TARGET register, is automatically optimized to maximize ADC dynamic range, once AGC lock has occurred. This improves performance in channels where the interference produces non-gaussian distribution in the sampled input signal, such as channels with large amounts of PAL ACI. This is not recommended for use with dual AGC control in ZIF mode. RESET: 0x0C Default 00 0 R/W R/W R/W 4:1 AGCENHUPDATE 0110 R/W 0 AGC ENHENABLE 0 R/W AGC_MEAN_CX Offset Address: 0x53 Bit 7:4 3:0 Name Reserved AGCMEANCX Read/Write Description Sets the mean value of threshold crossings in enhanced AGC algorithm. This value determines the number of times a sample can exceed an internal threshold before the AGC target value is decreased. The recommended value is "4". RESET: 0x04 Default 0000 0100 R/W R/W R/W AGC_BWREDOFFSET Offset Address: 0x54 Bit 7:4 3:0 Name Reserved AGCBWREDOFFSET Read/Write Description AGC bandwidth reduction offset. Sets a base level AGC gain reduction which is reduced further by AGC_CTL (AGC BW Reduction) after AGC lock is achieved. RESET: 0x0A Default 0000 1010 R/W R/W R/W Note) 1. Higher values result in lower gains, lower bandwidth and longer acquisition times. 2. Lower values result in higher gains, higher bandwidth and shorter acquisition times. 3. To prevent excessive AGC gain fluctuation from too high a bandwidth, it is recommended that the sum of AGCBWREDOFFSET and AGC_CTL(AGC BW Reduction) should exceed 4. The default of AGCBWREDOFFSET = 10 maintains compatibility with the CXD1973Q. - 71 - CXD1968AR AGC_MINGAIN Offset Address: 0x55 Bit 7:0 Name AGCMINGAIN Read/Write Description AGC minimum gain. Sets a minimum gain limit for the IFAGC output. This register is a signed 8-bit value which sets the minimum gain according to the table below. RESET: 0x80 Default 80h R/W R/W Note) 1. MinGain is the minimum gain limit required at the IFAGC output, scaled to a 12-bit or 10-bit signed value depending upon the AGC resolution set in the AGC_PWM_ENH_CTL register. AGC resolution (bits) 12 12 10 10 AGC_CTL (AGC_NEG) 0 1 0 1 AGCMINGAIN MinGain / 16 -MinGain / 16 MinGain / 4 -MinGain / 4 Example using 12-bit AGC with positive gain polarity: Where the IFAGC output gain range is from -2048 (low gain) to +2047 (high gain) in 12-bit AGC mode with AGC_CTL (AGC_NEG) = 0, and the minimum gain is to be limited to -1024. AGCMINGAIN = -1024/16 = -64 Example using 10-bit AGC with negative gain polarity: Where the IFAGC output gain range is from +512 (low gain) to -512 (high gain) in 10-bit AGC mode with AGC_CTL (AGC_NEG) = 1, and the minimum gain is to be limited to 256. AGCMINGAIN = -256/4 = -64 2. The default value of -128 is compatible with the CXD1973Q giving full AGC gain range with no limiting. AGC_MODIFIED_TARGET_I Offset Address: 0x56 Bit Name Read Only Description Default R/W 7:0 AGC_MODIFIED_ TARGET_I When the AGC is "not locked", this register will read back the user requested AGC target value as set in the AGC_TARGET register. When the AGC is "locked" (and the AGC_ENHANCED_ENABLE bit is set active high in the AGC_PWM_ENH_CTL register), this register will contain the top 8 MSBs of the internally modified AGC target value as dictated by the I channel conditions. -- R - 72 - CXD1968AR SYR_MISC4 Offset Address: 0x57 Bit 7:4 3:0 Name CCS Count Limit MP Moved Count Limit Read/Write Description Sets CCS count limit. If zero, the CCS filter remains on once enabled by the enhanced tracker. Sets MP moved count limit. The maximum number of enhanced symbol tracker periods for automatic update. Set to "0" to disable this functionality. RESET: 0x03 Default 0000 0011 R/W R/W R/W SYR_NUMBINSLOOKBACK Offset Address: 0x58 Bit 7:6 5:0 Name Reserved NumBinsLookBack Read/Write Description RESET: 0x0F Default 00 R/W R/W R/W Sets the range over which to search for each new update to the FFT window start time during each enhanced tracker tracking period. 0Fh - 73 - CXD1968AR Registers new to CXD1968AR SYR_CPLXMFENABLE Offset Address: 0x59 Bit 7 6 5 4 3 2 1 0 8K 1/4 8K 1/8 8K 1/16 8K 1/32 2K 1/4 2K 1/8 2K 1/16 2K 1/32 Enables complex matched filtering for the enhanced tracker in the named modes. Improves doppler channel performance. Name Description Default 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write RESET: 0xFF TEST10 Offset Address: 0x5A Bit 7:4 3 2 1 0 Name Reserved TEST10[3] TEST10[2] TEST10[1] TEST10[0] Read/Write Description RESET: 0x0F Default 0 1 1 1 1 R/W R/W R/W R/W R/W R/W TEST11 Offset Address: 0x5B Bit 7:6 5:0 Name Reserved TEST11[5:0] Read/Write Description RESET: 0x10 Default 00 10h R/W R/W R/W - 74 - CXD1968AR SYR_MISC5 Offset Address: 0x5C Bit 7 6:4 3 2 1 0 Name SKIRTRMV NUMSYMSFTRACK_LUT POST ECHO EXT ENABLE NTTRACK CHC FFT 512 ECHO STRETCH Read/Write Description Enables removal of skirt in enhanced tracking mode. Must be set to "7" in the CXD1968AR. Set to "0" to enable a longer observation period before responding to emerging pre-echoes. Controls re-computations inside enhanced tracker. Enables use of 512 point IFFT in enhanced tracker. Enables support for automatically detecting and tracking echoes outside the guard interval. RESET: 0x79 Default 0 111 1 0 0 1 R/W R/W R/W R/W R/W R/W R/W Note) Use Sony recommended settings for this register. AGC_MOD_TARGET_Q Offset Address: 0x5F Bit Name Read Only Description When the AGC is "not locked", this register will read back the user requested AGC target value as set in the AGC_TARGET register. When the AGC is "locked" (and the AGC_ENHANCED_ENABLE bit is set active high in the AGC_PWM_ENH_CTL register), this register will contain the top 8 MSBs of the internally modified AGC target value as dictated by the Q channel conditions. Default R/W 7:0 AGC_MODIFIED_ TARGET_Q -- R AGC_GAIN_3 Offset Address: 0x60 Bit 7:0 Name AGC_GAIN_Q Read Only Description Current (or latched) AGC gain bits 7:0 for the Q channel Default -- R/W R AGC_GAIN_4 Offset Address: 0x61 Bit 7:4 3:0 Name Reserved AGC_GAIN_Q Read Only Description Current (or latched) AGC gain bits 11:8 for the Q channel Default -- -- R/W R R - 75 - CXD1968AR QIC_MISC1 Offset Address: 0x62 Bit 7:4 3 Name Reserved QIC ENABLE Read/Write Description If set, enables the IQ phase imbalance (non-frequency selective) detection/correction. This bit should be set when using ZIF tuners to correct I/Q phase imbalance. Sets the loop gain value of the IQ phase imbalance corrector: smaller values speed up the convergence rate. QIC_GAIN 000 001 010 011 100 101 110 111 Loop gain value 1/256 1/512 1/1024 1/2048 1/4096 1/8192 1/16,384 1/32,768 RESET: 0x0B Default 0 1 R/W R/W R/W 2:0 QIC_GAIN 011 R/W QIC_IQPHASEERR Offset Address: 0x63 Bit 7:0 Name IQPhaseErr Read Description Detected IQ phase imbalance value. Phase imbalance (Degrees) = IQPhaseErr / 4 Default -- 0x00 R/W R TRL_NOMINALRATE_0 Offset Address: 0x65 Bit 7:0 Name TRL Nominal Rate Read/Write Description Bits 7:0 of TRL nominal rate Default 00 0x00 R/W R/W Note) 1. The TRL_NOMINALRATE is a 24-bit non-contiguous register comprising three 8-bit registers called TRL_NOMINALRATE_2, TRL_NOMINALRATE_1 and TRL_NOMINALRATE_0. 2. Also see TRL_NOMINALRATE_1 at address 0x1B and TRL_NOMINALRATE_2 at address 0x1C. - 76 - CXD1968AR CHC_LEAKAGE Offset Address: 0x6B Bit 7:4 Name Reserved Read/Write Description CHC correction factor for doppler channels. If CHC_LEAKAGE set to "0", no correction is applied. otherwise; Correction factor = 1 / [2(CHC_LEAKAGE + 2)] ie. For CHC_LEAKAGE = 11 (default); Correction factor = 1/8192 RESET: 0x0B Default 0 R/W R/W 3:0 CHC_LEAKAGE Bh R/W TEST1 Offset Address: 0x6C Bit 7:1 0 Name Reserved TEST1[0] Test use only Read/Write Description RESET: 0x00 Default 0 0 R/W R/W R/W TEST2 Offset Address: 0x6D Bit 7:0 Name TEST[7:0] Test use only Read/Write Description RESET: 0x00 Default 00 R/W R/W TEST3 Offset Address: 0x70 Bit 7 6:5 4:0 Name TEST3[7] Reserved TEST3[4:0] Test use only Test use only Read/Write Description RESET: 0x0A Default 0 00 Ah R/W R/W R/W R/W TEST4 Offset Address: 0x71 Bit 7:0 Name TEST[7:0] Test use only Read Only Description Default -- R/W R - 77 - CXD1968AR TEST5 Offset Address: 0x72 Bit 7:0 Name TEST5[7:0] Test use only Read Only Description Default -- R/W R TEST6 Offset Address: 0x73 Bit 7:0 Name TEST6[7:0] Test use only Read Only Description Default -- R/W R TEST7 Offset Address: 0x74 Bit 7:0 Name TEST7[7:0] Test use only Read/Write Description RESET: 0x00 Default 00h R/W R/W TEST8 Offset Address: 0x75 Bit 7:0 Name TEST8[7:0] Test use only Read/Write Description RESET: 0xFF Default FFh R/W R/W AUTORCV_1 Offset Address: 0x76 Bit 7 6:0 Name Reserved PRESCALE_VAL Read/Write Description Used to define the number of clock periods contained in a 1s time interval, for use by the auto-recovery state machine. Will allow definitions for up to 127MHz logic clock frequencies, where logic clock frequency = 2 x ADC clock frequency. RESET: 0x29 Default 0 29h R/W R/W R/W - 78 - CXD1968AR AUTORCV_2 Offset Address: 0x77 Bit 7 Name ACTIVATE Read/Write Description When set, this bit will activate the auto-recovery functionality. Used to differentiate between channel scanning (setup mode) and channel zapping (user mode). When set to "1", this specifies the scanning mode. When cleared to "0", this specifies zapping mode. The delay specified here will be used as the waiting time before advancing the auto-recovery state machine to the demodulator acquisition state. 00: 7ms delay 01: 49ms delay 10: 119ms delay 11: 147ms delay This value specifies the maximum delay required to achieve a TPS-data locked indication once the tuner is settled, (2K mode ONLY, using 7ms increments). Timeouts for the 8K mode are calculated automatically by the CXD1968AR using this 2K timeout value, as shown below. RESET: 0x18 Default 0 R/W R/W 6 SCANNING 0 R/W 5:4 XMS_TUNER_WAIT 01 R/W 3:0 DEMOD_TIMEOUT_2K 2K mode Maximum AGC lock time + 235 symbols 47ms + 65.8ms Timeout value for "demod_timeout_2k" = 66/7ms 9. TPS_demod_timeout for 8K = AGC_lock time + [demod_timeout_2K x 4] The recommended value for the "demod_timeout_2k" register is 9h (1001'b). 1000 R/W Note) The table below describes the receiver mode of operation with respect to the values contained in the coreactive bit (0x00, bit5) and the activate AR bit (0x77 bit7). Coreactive 0 0 1 1 AR active 0 1 0 1 Description Chip idle (as in the CXD1973Q/CXD1976R) Auto-recovery state machine active Ordinary/Default manual mode active (as in the CXD1973Q/CXD1976R) User has programed core active as well as setting AR active. Autorecovery will take over control, but this is not a recommended mode of use. CSF_MISC Offset Address: 0x78 Bit 7:1 0 Name Reserved CSF_ENABLE TBD Read/Write Description If set, channel selection filter enabled. RESET: 0x01 Default 0 1 R/W R/W R/W - 79 - CXD1968AR AUTORCV_3 Offset Address: 0x79 Bit 7:5 Name Reserved TBD Read/Write Description This value represents the maximum allowable delay for achieving a TS lock indication, after a TPS locked indication has been achieved. Worst case delay = 204 symbols (8K) + 38 packets @ 5M baud = 195ms (= 28 using 7ms increments) RESET: 0x1C Default 000 R/W R/W 4:0 TS_LOCK_TIMEOUT 11100 R/W AUTORCV_4 Offset Address: 0x7A Bit 7:4 Name AUTORCV_RESERVED TBD Read Only Description This signifies the current status of the demodulator as reported by the auto-recovery state machine. BIT 0: When set, reports that the TPS status can now be read (TPS_STATUS_READY). Default -- R/W R 3:0 DEMOD_STATUS BIT 1: When set, reports that the TS status can now be read (TS_STATUS_READY). BIT 2: When set, reports TPS lock achieved. When cleared, reports TPS lock NOT achieved. Only valid when bit 0 is set. BIT 3: When set, reports TS lock achieved. When cleared, reports TS lock NOT achieved. Only valid when bit 1 is set. -- R TPS_RESERVED_1_EVEN Offset Address: 0x7B Bit 7:0 Name CELLID[7:0] Read Only Description TPS reserved bits S40-S47 representing Cell-ID bits 7:0 respectively, received in TPS frame numbers 2 and 4. Default -- R/W R - 80 - CXD1968AR TPS_RESERVED_2_EVEN Offset Address: 0x7C Bit 7:6 5 Reserved TimeSlicedData Name Not used Read Only Description TPS reserved bit S48 - DVB-H time sliced data present in received data. In hierarchical mode, these bits correspond to LP stream. TPS reserved bit S49 - DVB-H MPE-FEC encoded data present in received data. In hierarchical mode, these bits correspond to LP stream. TPS reserved bits S50-S53 received during TPS frame numbers 2 and 4. Default -- -- Bit R R 4 3:0 MPE-FECData TPS_RESERVED_EVEN -- -- R R DCC_OFFSET_I Offset Address: 0x7D Bit 7:0 Name DCC_OFFSET_I Read Only Description Detected DC offset value on the I channel (signed) Default -- R/W R DCC_OFFSET_Q Offset Address: 0x7E Bit 7:0 Name DCC_OFFSET_Q Read Only Description Detected DC offset value on the Q channel (signed) Default -- R/W R DCC_MISC Offset Address: 0x7F Bit 7:3 Name RESERVED Read/Write Description Sets the DCC gain value as indicated in the table below: Register value 2K Mode 8K Mode 2-18 0 2-16 1 2-17 2-19 2 2-18 2-20 -19 3 2 2-21 RESET: 0x03 Default 00000 R/W R/W 2:1 DCC_GAIN 01 R/W 0 DCC_ENABLE If set, DC offset cancellation is enabled. This bit should be set when using DC-coupled ZIF tuners. 1 R/W - 81 - CXD1968AR FEC Registers FEC_PARAMS Offset Address: 0x80 Bit Name Description If the TSCLK output is gated (bit Tsclk_full of BBPARAMS low) and TS smoothing enabled (bit ENABLE of SMOOTH_CTRL high), then setting this bit ensures that the TSCLK output remains active during any gap in the TS output. 0: TSCLK inactive during gaps 1: TSCLK active during gaps 6 Auto_clear Auto clearing of Interrupt flag. 0: Auto clear disabled 1: Auto clear enabled When the transport stream is operating in its serial mode (see bit 4 below) this bit controls on which TSDATA bit the serial data is presented. 0: Data is presented on TSDATA[0] 1: Data is presented on TSDATA[7] Determines whether the parallel or serial interface for the transport stream is selected. 4 TS_parallel_sel 0: Serial interface selected 1: Parallel interface selected When serial interface selected, Pins TSDATA[7] or TSDATA[0] (see bit 5 above) drive the serial data. Selects whether the most significant bit of a byte is presented on TSDATA bit[7] or bit[0]. In serial mode this bit selects whether the most significant bit is presented as the first or last bit of a byte. 0: MSB is TSDATA[0] (last bit, serial mode). 1: MSB is TSDATA[7] (first bit, serial mode). Selects BER Measurement or Estimation. 2 Measurement_Sel 0: Estimation 1: Measurement When Measurement is selected, the RS_DISABLE bit must also be set to enable BER measurement to be made. Tri-states transport stream outputs (serial and parallel). 1 Tri_State_Outputs 0: Outputs driven 1: Outputs tri-state Enables/Disables RS decoder. 0 RS_Disable 0: Enables error correction 1: Passes data without correction 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W Read/Write RESET: 0x1A fec_param reset Default R/W 7 Tsclk_cont 0 R/W 5 Ser_data_on_msb 0 R/W 3 Output_Sel_Msb 1 R/W - 82 - CXD1968AR BB_PARAMS Offset Address: 0x81 Bit 7 Name Tsvalid_Active_High 0: Active low 1: Active high Read/Write Description Determines the sense of TSVALID. RESET: 0xF0 fec_param reset Default 1 R/W R/W Determines the sense of TSSYNC. 6 Tssync_Active_High 0: Active low 1: Active high Determines the sense of TSERR. 5 Tserr_Active_High 0: Active low 1: Active high Selects whether TSDATA should be sampled on the positive or negative edge of TSCLK. 0: Negative edge 1: Positive edge Determines the behavior of TSCLK in gated mode (when Tsclk_full is RESET). 3 Tsclk_204 0: TSCLK is active for only the first 188 bytes in the TS packet. 1: TSCLK is active for all 204 bytes in the TS packet. Determines the behavior of the TSSYNC output in both parallel and serial mode. 2 Tssync_byte 0: Active only for the first bit in the sync byte (use only in serial mode) 1: Active for the entire sync byte (recommended for parallel or serial modes) Determines whether TSERR is valid for 204 bytes of the TS packet or for 188 bytes. Used only when bit 2 is not set. 0: 188 bytes 1: 204 bytes Determines whether TSCLK is active continuously or is only active for valid data. 0: Gated 1: Continuous 0 R/W 0 R/W 1 R/W 1 R/W 4 Latch_on_posedge 1 R/W 1 Tserr_full 0 R/W 0 Tsclk_full 0 R/W Note) It may be necessary to set bit 2 for compatibility with standard MPEG-2 decoders. BER_PERIOD Offset Address: 0x83 Bit 7:6 5 Name Reserved Read/Write Description Used to configure BEREST block for test. RESET: 0x04 Default 00 R/W R/W R/W Berest_test_mode 0: Normal mode 1: Test mode Bit error rate estimation/measurement period. Min. 0x01, Max. 0x15 Estim./measurement period = 2BER_EST_PERIOD x 204-byte packets 0 4:0 Ber_Est_Period[4:0] 00100 R/W - 83 - CXD1968AR FEC_STATUS Offset Address: 0x84 Bit 7 Name Ber_ses Read Only Description 1: When a severely errored second is detected, i.e. when n or more 204-byte packets are uncorrectable in a second. n is defined by the LT_QLTY_THRESHOLD register. 1: When 1 or more 204-byte packets are uncorrectable in a second. (Note: An uncorrectable error occurs when more than 8 error bytes are present in a single packet.) 1: When FEC locked. When n SYNC bytes have been detected (n is programmable and defined by the SET_SYNC_DETECT register). 1: When transport stream lock lost condition detected. This occurs when n SYNC bytes go undetected (n is programmable and defined by the SET_SYNC_DETECT register). 1: When transport stream lock condition detected. Valid MPEG2 data is generated by the device from this time. 1: When viterbi synchronization condition detected. Viterbi synchronization operation controlled by VIT_SN and VIT_ST registers. 1: When new bit error rate value is available. This bit is cleared by a register read operation. Default -- R/W R 6 Ber_es -- R 5 Lck_Flag -- R 4 Ts_Llck_Flag -- R 3 2 1 0 Ts_Synch_Lock Vtb_Sync New_Ber_es Reserved -- -- -- -- R R R R SET_SYNC_DETECT Offset Address: 0x86 Bit Name Read/Write Description Controls whether the pre-RS decoder sync detect count is decremented or reset when a missing sync byte is detected while locking. 0: Reset 1: Decrement Controls whether the post-RS decoder sync detect count is decremented or reset when a missing sync byte is detected. 0: Reset 1: Decrement RESET: 0xD6 Default R/W 7 Synch_Cntr_Mode 1 R/W 6 Ts_Synch_Cntr_Mode 1 R/W 5:3 2:0 Sync_Loss_Lddr_Length[2:0] Synch_Lddr_Lngth[2:0] Sync byte counter threshold at which lock is lost (post-RS decoder only). Sync byte counter threshold at which lock is achieved (pre- and post-RS decoder). 010 110 R/W - 84 - CXD1968AR LT_QLTY_THRESHOLD Offset Address: 0x87 Bit 7:0 Name LT_QLTY_THRESHOLD[7:0] Read/Write Description Long term quality threshold. Used for detecting severely errored second flag. RESET: 0x04 Default 04h R/W R/W BER_ESTIMATE_0 Offset Address: 0x88 Bit 7 Name BERCNT Read Only Description Bits 7:0 of measured/estimated BER Default -- R/W R BER_ESTIMATE_1 Offset Address: 0x89 Bit 7 Name BERCNT Read Only Description Bits 15:8 of measured/estimated BER Default -- R/W R BER_ESTIMATE_2 Offset Address: 0x8A Bit 7 6:5 4 3:0 Name New_Estimate Reserved BERCNT_overflow BERCNT Read Only Description Set at the end of the BER measurement period. This bit is reset by performing a read operation to the BER_ESTIMATE_2 register. 1: Indicates that the internal bit error counter has overflowed. Bits 19:16 of measured/estimated BER Default -- -- -- -- R/W R R R R CWRJCT_CNT_0 Offset Address: 0x8B Bit 7:0 Name CWRJCT_CNT Read Only Description Bits 7:0 of number of rejected codewords (MPEG2 packets) in a second Default -- R/W R CWRJCT_CNT_1 Offset Address: 0x8C Bit 7:0 Name CWRJCT_CNT Read Only Description Bits 15:8 of number of rejected codewords (MPEG2 packets) in a second Default -- R/W R - 85 - CXD1968AR VIT_CTRL Offset Address: 0x90 Bit 7 Name Rate_Sel Read/Write Description Selects puncturing rate from the register or from TPS data. 0: TPS data 1: Register value Sets the puncturing rate. 000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101 to 111: Auto Defines sampling period in I/Q samples for bit error rate in the Viterbi decoder. 000: 28 001: 213 010: 214 011: 215 100: 216 101: 217 110: 218 111: 219 RESET: 0x11 Default 0 R/W R/W 6:4 Rate[2:0] 001 R/W 3 Reserved 0 R/W 2:0 Bert[2:0] 001 R/W Note) It is recommended that the value of VIT_CTRL bit 7 should be "0". VIT_SN Offset Address: 0x91 Bit 7:5 4:0 Name Reserved SN[9:5] Read/Write Description Sets threshold for estimation of Viterbi synchronization. Threshold = SN x 32 (Min. 32, Max. 992) RESET: 0x1F Default 000 11111 R/W R/W R/W VIT_ST Offset Address: 0x92 Bit 7:4 3:0 Name Reserved ST[12:9] Read/Write Description Sets the sampling period for Viterbi synchronization Sampling period = ST x 512 (Min. 512, Max. 6656) RESET: 0x00 Default 0000 0000 R/W R/W R/W - 86 - CXD1968AR VIT_BER_1 Offset Address: 0x93 Bit 7:0 VBER Name Read Only Description Bits 7:0 of Viterbi bit error count Default -- R/W R VIT_BER_2 Offset Address: 0x94 Bit 7:0 VBER Name Read Only Description Bits 15:8 of Viterbi bit error count Default -- R/W R - 87 - CXD1968AR Miscellaneous Registers CHIP_INFO Offset Address: 0xA0 Bit 7:2 1:0 Name CHIP Ident Version Chip version number Description Chip identification number Default 011000 01 R/W R R Read Only RESET: 0x61 Note) This register cannot be read back until the PLL has been enabled. RST_REG Offset Address: 0xA2 Bit 7 Name adc_rst ADC reset enable. Read/Write Description 1: Enable ADC reset when cold reset is active. COFDM demodulator core reset enable. 1: Enable COFDM demodulator reset when warm or cold reset is active. Viterbi reset enable. 1: Enable Viterbi reset when warm or cold reset is active or when the auto recovery mode is selected. FEC (excluding Viterbi) reset. 1: Enable FEC (excluding Viterbi) reset when warm or cold reset is active or when the auto recovery mode is selected. Set when RESETN pin of device is driven active. RESET: 0x04 Default 0 R/W R/W 6 cofdm_rst 0 R/W 5 Vit_rst 0 R/W 4 fec_rst 0 R/W 3 2 1 0 Reserved Hard Cold Warm 0: Release after power-on reset (after PLL is stable) 1: No effect Cold reset. Warm reset. 1: Reset 1: Reset 0 1 0 0 R/W R/W R/W R/W Note) Software must wait 500s for the PLL to stabilize before setting RST_REG bit 2. INTERRUPT_SOURCE Offset Address: 0xA3 Bit 7 6 5 4 3 2 1 0 Name Ts_if_int Cofdm_Int Ts_synch_Lock Ts_Llck_Flag Reserved Ber_Es Ber_Ses Rs_cwrjct_Flag Read/Write Description 1: TS smoothing buffer overflow or underflow detected. 1: COFDM demodulator core Interrupt. 1: Transport stream locked. 1: Transport stream lock lost. 1: Errored second detected. 1: Severely errored second detected. 1: More than 8 error bytes in current packet. RESET: 0x00 Default 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Note) Each bit may be cleared by writing a "1" to the appropriate bit location. - 88 - CXD1968AR INTERRUPT_MASK Offset Address: 0xA4 Bit 7 6 5 4 3 2 1 0 Name Ts_if_int_En Cofdm_Int_En Ts_synch_Lock_En Ts_Llck_Flag_En Reserved Ber_Es_En Ber_Ses_En Rs_cwrjct_Flag_En Read/Write Description 1: Enable TS interface interrupts. 1: Enable COFDM demodulator core interrupts. 1: Enable TS lock interrupt. 1: Enable TS lost lock interrupt. 1: Enable second error interrupt. 1: Enable second severity error interrupt. 1: Enable codeword reject interrupt. RESET: 0x00 Default 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W TIMEOUT_VAL Offset Address: 0xA6 Bit 7:0 Name TIMEOUT_VAL[7:0] Read/Write Description Sets the time after which the CXD1968AR will timeout an I2C access when waiting for an I2C master response. The timeout period can be set to between approximately 2 and 500ms represented by 00h and FFh in this register. RESET: 0xFF Default FFh R/W R/W PLL_FODR Offset Address: 0xA7 Bit 7 6:5 Name Reserved OD[1:0] 00: Not allowed 01: 1 10: 2 11: 4 Read/Write Description RESET: 0x62 Default 0 R/W R/W R/W PLL output divider. Default value for OD[1:0] is 03h. Yielding a value of 4 for NO. 11 PLL input divider. Controls comparison frequency FREF. 4:0 R[4:0] FREF = FIN / NR - Valid range is 2MHz to 8MHz. NR = 16 x R4 + 8 x R3 + 4 x R2 + 2 x R1 + R0 Default value for R[4:0] is 0x02. Yielding a value of 2 for NR. Note) PLL output frequency FOUT = (FIN x NF / (NR x NO) Where FIN is the frequency of the clock signal present on the XTALI pin. 00010 R/W - 89 - CXD1968AR PLL_F Offset Address: 0xA8 Bit Name Read/Write Description PLL feedback divider bits 7 to 0. FVCO = FREF x NF - Valid range is 200MHz to 400MHz. NF = 2 x (128 x F7 + 64 x F6 + 32 x F5 + 16 x F4 + 8 x F3 + 4 x F2 + 2 x F1 + F0) Default value for F[7:0] is 0x52. Yielding a value of 164 for NF. RESET: 0x52 Default R/W 7:0 F[7:0] 52h R/W The above register defaults are for 4MHz crystal operation. The table below shows the suggested PLL settings when using other crystal frequencies. Xtal Freq [MHz] 4.00 8.00 16.00 20.48 OD[1:0] 3 3 3 3 R[4:0] 2 4 8 10 decimal F[7:0] 82 decimal 82 decimal 82 decimal 80 decimal PLL_FODR 0x62 0x64 0x68 0x6A PLL_F 0x52 0x52 0x52 0x50 PLL_CONTROL Offset Address: 0xA9 Bit 7 6 5 4 3 2 1 0 Name Reserved PLL_power_down PLL_op_enable PLL_bypass ext_clk_enable PLL_op_invert PLL_test_mode clock_disable Read/Write Description 1: Power down the PLL. 1: Enable the PLL output clocks. 1: Bypass the PLL generated clock and use external clock source. 1: Enables the external fast clock (instead of the PLL). 1: Inverts the PLL output clocks. 1: Puts the PLL in test mode. 1: Disables most of the clocks (for low noise ADC evaluation). RESET: 0x40 Default 0 1 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W TUNER_CTRL5 Offset Address: 0xAF Bit 7 6 5 4 3:2 1 0 Name enable_quiet_I2C Reserved Reserved Reserved Reserved Reserved Reserved Read/Write Description 0: Tuner Quiet I2C bus disabled. 1: Tuner Quiet I2C bus enabled. RESET: 0x00 Default 0 0 0 R/W NB: Do not set to "1". NB: Do not set to "1". NB: Do not set to "1". 0 00 0 0 R/W R/W R/W - 90 - CXD1968AR AUTO_RESET Offset Address: 0xB1 Bit 7:1 0 Disable Name Reserved Read/Write Description 1: Disable auto reset of the FEC on code rate change. RESET: 0x01 Default 00h 1 R/W R/W R/W RF_IFAGC_CTRL0 Offset Address: 0xB2 Bit 7:6 5 4 Name RF_IFAGCQ_PWM Reserved IF_AGC_EN Read/Write Description RF_AGC_PWM bits 1:0 0: IF_AGC is tri-state. 1: IF_AGC is driven. 00: Tri-state mode - RF_IFAGC_Q is a GPI pin. 01: Manual PWM mode for RF_IFAGC_Q output 10: GPO mode for RF_IFAGC_Q output set by bit 1 this reg 11: ZIF mode: Automatic PWM mode for Q channel AGC o/p 0: RF_IFAGC_Q output 0 when GPO mode selected 1: RF_IFAGC_Q output 1 when GPO mode selected Senses state of RF_IFAGC_Q input pin level. 0: RF_IFAGC_Q input at logic 0 1: RF_IFAGC_Q input at logic 1 RESET: 0x11 Default 00 0 1 R/W R/W R/W R/W 3:2 RF_IFAGCQ_MODE 00 1 RF_IFAGCQ_GPO 0 R/W 0 RF_IFAGCQ_GPI 1 R RF_IFAGCQ_CTRL1 Offset Address: 0xB3 Bit 7:0 Name RF_IFAGCQ_PWM Read/Write Description RF_AGC_PWM bits 9:2 RESET: 0x00 Default 00h R/W R/W Note) 1. In the time interval between host writes to RF_IFAGCQ_CTRL0 and RF_IFAGCQ_CTRL1, the manual control to the AGC will have an intermediate value. 2. The ability to use the RFAGC output as a PWM output or a GPIO has been added to the CXD1968AR compared to the CXD1973Q. RF_AGC_CTRL0[2:1] that were previously reserved bits are now used for this purpose. 3. RF_IFAGCQ_PWM is a straight binary value. - 91 - CXD1968AR SMOOTH_CTRL Offset Address: 0xB4 Bit 7:6 5:3 2 Name CHANNEL_WIDTH Reserved RESET Read/Write Description 00: 8MHz channel 01: 7MHz channel 10: 6MHz channel 11: Reserved Channel width RESET: 0x04 Default 00 000 R/W R/W R/W R/W 0: Smoothing circuit not in its reset state 1: Smoothing circuit is held in its reset state 0: Data period value can be updated manually (via I2C) or left at its default setting. 1: Update data period value automatically from received TPS information. 0: Disable smoothing circuit. When disabled, the input to the smoothing circuit is routed to the output without going through the smoothing FIFO. 1: Enable smoothing circuit. 1 1 DATA_PERIOD_AUTO 0 R/W 0 ENABLE 0 R/W SMOOTH_STAT Offset Address: 0xB5 Bit 7:2 Name Reserved Read/Write Description 1: An underflow condition has been detected. An underflow condition is where data is requested but cannot be provided because the read FIFO is empty. RESET: 0x00 Default 00h R/W R/W 1 UNDERFLOW Note that when data is requested but not provided because the next TS word is a sync-byte and the FIFO does not contain a complete TS packet, this condition is part of the smoothing blocks normal operation and is not classed as an underflow condition. Write a "1" to this location to clear this bit. 1: An overflow condition has been detected. Write a "1" to this location to clear this bit. 0 R/W 0 OVERFLOW 0 R/W SMOOTH_DELAY Offset Address: 0xB6 Bit Name Read/Write Description The value in this register represents the data path delay in transport stream packets between the COFDM core and the data smoothing block. This information is used by the smoothing circuit to determine the delay between TPS bit changes and the associated modification to the transport stream output data rate. RESET: 0x14 Default Bit 7:0 DELAY 14h R/W - 92 - CXD1968AR SMOOTH_DP0 Offset Address: 0xB7 Bit Name Read/Write Description This part of the data period value represents the fractional number of clock periods per TS word. A read from the SMOOTH_DP0 register returns the current value of the fractional part of the data period value. A read from SMOOTH_DP0 also causes the current value of the integer part of the data period value to be stored in a holding register, which can be accessed by reading from SMOOTH_DP1. RESET: 0x80 Default R/W 7:0 DATA_PERIOD[7:0] Writing to SMOOTH_DP0 only has an effect when the DATA_PERIOD_AUTO bit of the SMOOTH_CTRL register is set to "0". In this case, writing to SMOOTH_DP0 has the effect of storing the 8-bit value in a holding register. Writing to SMOOTH_DP1 then has the effect of transferring data from the holding register to the SMOOTH_DP0 register proper. For these reasons SMOOTH_DP0 and SMOOTH_DP1 should be read from or written to in order, SMOOTH_DP0 first. 80h R/W SMOOTH_DP1 Offset Address: 0xB8 Bit Name Read/Write Description This part of the data period value represents the integer number of clock periods per TS word. A read from the SMOOTH_DP1 register returns the integer part of the data period value previously stored in a holding register when a read from the SMOOTH_DP0 register occurred (see SMOOTH_DP0 above). RESET: 0x09 Default R/W 7:0 DATA_PERIOD[15:8] Writing to SMOOTH_DP1 only has an effect when the DATA_PERIOD_AUTO bit of the SMOOTH_CTRL register is set to "0". In this case, writing to SMOOTH_DP1 has the expected effect of updating the SMOOTH_DP1 register value, and has the additional effect of transferring data from a holding register (updated during a SMOOTH_DP0 write operation) into the SMOOTH_DP0 register (see SMOOTH_DP0 above). 09h R/W - 93 - CXD1968AR ADC_CONTROL Offset Address: 0xB9 Bit 7 6 5 4 3 2 1 0 Name REFPD_Q STDBY_Q RESET_Q PWRDN_Q REFPD_I STDBY_I RESET_I PWRDN_I Read/Write Description Set to "1" to power down reference in Q channel ADC. Set to "1" to put the Q channel ADC in standby mode. Q channel ADC is reset by writing a "0" or "1" sequence to this bit. Set to "1" to power down the Q channel ADC. Set to "1" to power down reference in I channel ADC. Set to "1" to put the ADC_I in standby mode. I channel ADC is reset by writing a "0" or "1" sequence to this bit. Set to "1" to power down the I channel ADC. RESET: 0xA2 Default 1 0 1 0 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Note) 1. Both ADCs are reset on power-up. 2. Before powering-down an ADC, ensure its respective reference is first powered-down. ADC_CONTROL2 Offset Address: 0xBA Bit Name Read/Write Description Selects reference voltage on ADC_I and ADC_Q. 00: refout = 0.35V 0.7V full scale diff p-p input 01: refout = 0.50V 1.0V full scale diff p-p input 10: refout = 0.75V 1.5V full scale diff p-p input 11: refout = 1.00V 2.0V full scale diff p-p input External A/D select. 0: Internal A/D selected 1: External A/D selected Selects internal ADC output type. 0: Offset binary: default for the CXD1968AR 1: 2's complement Used for testing ADC. 0: Normal mode 1: Test mode Enables ADC clock duty cycle correction. Sets pk-pk level of ADC sampling clock on ADC_I and ADC_Q. 0: 3.3V CMOS input level 1: 1.2V CMOS input level Enables driving of the ADC clock directly from XTALI input. 0: Normal mode (ADC clocked from PLL) 1: Direct clock mode RESET: 0x47 Default R/W 7:6 REFSEL[1:0] 01 R/W 5 Ext_A/D_Select 0 R/W 4 ADC_Offset_2s_Comp 0 R/W 3 2 ADC_test_mode DCCEN 0 1 R/W R/W 1 CLKRCVEN 1 R/W 0 ADC_DIRECT_CLKEN 1 Note) When using external A/D, the direct clock mode must be used. - 94 - CXD1968AR RAM_CONTROL Offset Address: 0xBC Bit 7:1 0 Name Reserved RAM_ STANDBY Read/Write Description Set to put all RAMs in standby mode. Used for low-power standby mode. RESET: 0x00 Default 00h 0 R/W R/W R/W ADC_CONTROL3 Offset Address: 0xBD Bit 7 Name RINTEN_Q Read/Write Description Enables internal bias current resistor for ADC_Q Selects value of internal bias current resistor if RINTEN_Q = 1. This can be used to optimize power consumption of ADC_Q according to max. sampling rate used. 000: 18k 001: 22k 010: 27.9k 011: 37.7k 100: 57.4 k 101: 77.1 k 110: 116.5k 111: 234.5k Enables internal bias current resistor for ADC_I. Selects value of internal bias current resistor if RINTEN_I = 1. This can be used to optimize power consumption of ADC_I according to max. sampling rate used. 000: 18k 001: 22k 010: 27.9k 011: 37.7k 100: 57.4 k 101: 77.1 k 110: 116.5k 111: 234.5k RESET: 0xFF Default 1 R/W R/W 6:4 RINTSEL_Q[2:0] 111 R/W 3 RINTEN_I 1 R/W 2:0 RINTSEL_I[2:0] 111 R/W - 95 - CXD1968AR ADC_STATUS Offset Address: 0xBE Bit 7 Name OVF_Q Read Only This register is cleared on a Write access Description Indicates overflow condition on ADC_Q input. 0: No overflow 1: Overflow of input Indicates underflow condition on ADC_Q input. 0: No underflow 1: Underflow of input Indicates overflow condition on ADC_I input. 0: No overflow 1: Overflow of input Indicates underflow condition on ADC_I input. 0: No underflow 1: Underflow of input R Default R/W 6 UDF_Q R 5 OVF_I R 4 3:0 UDF_I Reserved R - 96 - CXD1968AR Package Outline (Unit: mm) - 97 - Sony Corporation |
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